r_w_con.map.eqn

用Verilog实现8255芯片功能

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L9 is always1~0
--operation mode is normal

A1L9 = wr_n & (!rd_n);

--A1L01 is always1~8
--operation mode is normal

A1L01 = wr_n & (!rd_n);


--A1L03 is bus_con~54
--operation mode is normal

A1L03 = A1L9 & !a1 & !cs_n & !a0;

--A1L33 is bus_con~57
--operation mode is normal

A1L33 = A1L9 & !a1 & !cs_n & !a0;


--A1L13 is bus_con~55
--operation mode is normal

A1L13 = A1L9 & a0 & !a1 & !cs_n;

--A1L43 is bus_con~58
--operation mode is normal

A1L43 = A1L9 & a0 & !a1 & !cs_n;


--A1L23 is bus_con~56
--operation mode is normal

A1L23 = A1L9 & a1 & !cs_n & !a0;

--A1L53 is bus_con~59
--operation mode is normal

A1L53 = A1L9 & a1 & !cs_n & !a0;


--A1L04 is c_port~11
--operation mode is normal

A1L04 = a1 & (!cs_n & !a0);

--A1L14 is c_port~12
--operation mode is normal

A1L14 = a1 & (!cs_n & !a0);


--A1L84 is c_set_rst~0
--operation mode is normal

A1L84 = a1 & a0 & !con_word[7] & !cs_n;

--A1L94 is c_set_rst~10
--operation mode is normal

A1L94 = a1 & a0 & !con_word[7] & !cs_n;


--A1L32 is b_port~12
--operation mode is normal

A1L32 = a0 & (!a1 & !cs_n);

--A1L42 is b_port~13
--operation mode is normal

A1L42 = a0 & (!a1 & !cs_n);


--A1L7 is a_port~3
--operation mode is normal

A1L7 = !a1 & !cs_n & !a0;

--A1L8 is a_port~4
--operation mode is normal

A1L8 = !a1 & !cs_n & !a0;


--A1L17 is con~17
--operation mode is normal

A1L17 = a1 & a0 & (!cs_n);

--A1L27 is con~18
--operation mode is normal

A1L27 = a1 & a0 & (!cs_n);


--A1L31 is always3~59
--operation mode is normal

A1L31 = con_word[0] # con_word[1] # con_word[2] # con_word[3];

--A1L61 is always3~62
--operation mode is normal

A1L61 = con_word[0] # con_word[1] # con_word[2] # con_word[3];


--A1L41 is always3~60
--operation mode is normal

A1L41 = con_word[7] # con_word[6] # con_word[5] # con_word[4];

--A1L71 is always3~63
--operation mode is normal

A1L71 = con_word[7] # con_word[6] # con_word[5] # con_word[4];


--A1L51 is always3~61
--operation mode is normal

A1L51 = A1L31 # A1L41 # !rst_n;

--A1L81 is always3~64
--operation mode is normal

A1L81 = A1L31 # A1L41 # !rst_n;


--c_upper_io$latch is c_upper_io$latch
--operation mode is normal

c_upper_io$latch = A1L51 & con_word[3] # !A1L51 & (c_upper_io$latch) # !rst_n;

--A1L25 is c_upper_io$latch~3
--operation mode is normal

A1L25 = A1L51 & con_word[3] # !A1L51 & (c_upper_io$latch) # !rst_n;


--c_lower_io$latch is c_lower_io$latch
--operation mode is normal

c_lower_io$latch = A1L51 & con_word[0] # !A1L51 & (c_lower_io$latch) # !rst_n;

--A1L83 is c_lower_io$latch~3
--operation mode is normal

A1L83 = A1L51 & con_word[0] # !A1L51 & (c_lower_io$latch) # !rst_n;


--A1L11 is always2~5
--operation mode is normal

A1L11 = a1 & a0 & !cs_n # !rst_n;

--A1L21 is always2~20
--operation mode is normal

A1L21 = a1 & a0 & !cs_n # !rst_n;


--con_word[0] is con_word[0]
--operation mode is normal

con_word[0] = rst_n & (A1L11 & d_inbuf[0] # !A1L11 & (con_word[0]));

--A1L65 is con_word[0]~80
--operation mode is normal

A1L65 = rst_n & (A1L11 & d_inbuf[0] # !A1L11 & (con_word[0]));


--con_word[1] is con_word[1]
--operation mode is normal

con_word[1] = rst_n & (A1L11 & d_inbuf[1] # !A1L11 & (con_word[1]));

--A1L85 is con_word[1]~81
--operation mode is normal

A1L85 = rst_n & (A1L11 & d_inbuf[1] # !A1L11 & (con_word[1]));


--con_word[2] is con_word[2]
--operation mode is normal

con_word[2] = rst_n & (A1L11 & d_inbuf[2] # !A1L11 & (con_word[2]));

--A1L06 is con_word[2]~82
--operation mode is normal

A1L06 = rst_n & (A1L11 & d_inbuf[2] # !A1L11 & (con_word[2]));


--con_word[3] is con_word[3]
--operation mode is normal

con_word[3] = rst_n & (A1L11 & d_inbuf[3] # !A1L11 & (con_word[3]));

--A1L26 is con_word[3]~83
--operation mode is normal

A1L26 = rst_n & (A1L11 & d_inbuf[3] # !A1L11 & (con_word[3]));


--con_word[7] is con_word[7]
--operation mode is normal

con_word[7] = rst_n & (A1L11 & d_inbuf[7] # !A1L11 & (con_word[7]));

--A1L07 is con_word[7]~84
--operation mode is normal

A1L07 = rst_n & (A1L11 & d_inbuf[7] # !A1L11 & (con_word[7]));


--b_mode_io$latch is b_mode_io$latch
--operation mode is normal

b_mode_io$latch = A1L51 & con_word[1] # !A1L51 & (b_mode_io$latch) # !rst_n;

--A1L12 is b_mode_io$latch~3
--operation mode is normal

A1L12 = A1L51 & con_word[1] # !A1L51 & (b_mode_io$latch) # !rst_n;


--a_mode_io$latch is a_mode_io$latch
--operation mode is normal

a_mode_io$latch = A1L51 & con_word[4] # !A1L51 & (a_mode_io$latch) # !rst_n;

--A1L5 is a_mode_io$latch~3
--operation mode is normal

A1L5 = A1L51 & con_word[4] # !A1L51 & (a_mode_io$latch) # !rst_n;


--con_word[6] is con_word[6]
--operation mode is normal

con_word[6] = rst_n & (A1L11 & d_inbuf[6] # !A1L11 & (con_word[6]));

--A1L86 is con_word[6]~85
--operation mode is normal

A1L86 = rst_n & (A1L11 & d_inbuf[6] # !A1L11 & (con_word[6]));


--con_word[5] is con_word[5]
--operation mode is normal

con_word[5] = rst_n & (A1L11 & d_inbuf[5] # !A1L11 & (con_word[5]));

--A1L66 is con_word[5]~86
--operation mode is normal

A1L66 = rst_n & (A1L11 & d_inbuf[5] # !A1L11 & (con_word[5]));


--con_word[4] is con_word[4]
--operation mode is normal

con_word[4] = rst_n & (A1L11 & d_inbuf[4] # !A1L11 & (con_word[4]));

--A1L46 is con_word[4]~87
--operation mode is normal

A1L46 = rst_n & (A1L11 & d_inbuf[4] # !A1L11 & (con_word[4]));


--wr_n is wr_n
--operation mode is input

wr_n = INPUT();


--rd_n is rd_n
--operation mode is input

rd_n = INPUT();


--a1 is a1
--operation mode is input

a1 = INPUT();


--cs_n is cs_n
--operation mode is input

cs_n = INPUT();


--a0 is a0
--operation mode is input

a0 = INPUT();


--rst_n is rst_n
--operation mode is input

rst_n = INPUT();


--d_inbuf[0] is d_inbuf[0]
--operation mode is input

d_inbuf[0] = INPUT();


--d_inbuf[1] is d_inbuf[1]
--operation mode is input

d_inbuf[1] = INPUT();


--d_inbuf[2] is d_inbuf[2]
--operation mode is input

d_inbuf[2] = INPUT();


--d_inbuf[3] is d_inbuf[3]
--operation mode is input

d_inbuf[3] = INPUT();


--d_inbuf[7] is d_inbuf[7]
--operation mode is input

d_inbuf[7] = INPUT();


--d_inbuf[6] is d_inbuf[6]
--operation mode is input

d_inbuf[6] = INPUT();


--d_inbuf[5] is d_inbuf[5]
--operation mode is input

d_inbuf[5] = INPUT();


--d_inbuf[4] is d_inbuf[4]
--operation mode is input

d_inbuf[4] = INPUT();


--lk_bus is lk_bus
--operation mode is output

lk_bus = OUTPUT(A1L9);


--bus_con[0] is bus_con[0]
--operation mode is output

bus_con[0] = OUTPUT(A1L03);


--bus_con[1] is bus_con[1]
--operation mode is output

bus_con[1] = OUTPUT(A1L13);


--bus_con[2] is bus_con[2]
--operation mode is output

bus_con[2] = OUTPUT(A1L23);


--bus_con[3] is bus_con[3]
--operation mode is output

bus_con[3] = OUTPUT(!A1L9);


--r_w is r_w
--operation mode is output

r_w = OUTPUT(!A1L9);


--c_port is c_port
--operation mode is output

c_port = OUTPUT(A1L04);


--c_upper_io is c_upper_io
--operation mode is output

c_upper_io = OUTPUT(c_upper_io$latch);


--c_lower_io is c_lower_io
--operation mode is output

c_lower_io = OUTPUT(c_lower_io$latch);


--c_set_rst[0] is c_set_rst[0]
--operation mode is output

c_set_rst[0] = OUTPUT(con_word[0]);


--c_set_rst[1] is c_set_rst[1]
--operation mode is output

c_set_rst[1] = OUTPUT(con_word[1]);


--c_set_rst[2] is c_set_rst[2]
--operation mode is output

c_set_rst[2] = OUTPUT(con_word[2]);


--c_set_rst[3] is c_set_rst[3]
--operation mode is output

c_set_rst[3] = OUTPUT(con_word[3]);


--c_set_rst[4] is c_set_rst[4]
--operation mode is output

c_set_rst[4] = OUTPUT(A1L84);


--b_mode_io is b_mode_io
--operation mode is output

b_mode_io = OUTPUT(b_mode_io$latch);


--b_port is b_port
--operation mode is output

b_port = OUTPUT(A1L32);


--a_mode_io is a_mode_io
--operation mode is output

a_mode_io = OUTPUT(a_mode_io$latch);


--a_port is a_port
--operation mode is output

a_port = OUTPUT(A1L7);


--con is con
--operation mode is output

con = OUTPUT(A1L17);