r_w_con.map.summary

来自「用Verilog实现8255芯片功能」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Wed Nov 08 20:54:48 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : r_w_con
Top-level Entity Name : r_w_con
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 25
Total pins : 33
Total memory bits : 0
Total PLLs : 0