r_w_con.map.qmsg

用Verilog实现8255芯片功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 08 20:54:48 2006 " "Info: Processing started: Wed Nov 08 20:54:48 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off r_w_con -c r_w_con " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off r_w_con -c r_w_con" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "r_w_con.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file r_w_con.v" { { "Info" "ISGN_ENTITY_NAME" "1 r_w_con " "Info: Found entity 1: r_w_con" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "r_w_con " "Info: Elaborating entity \"r_w_con\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "con_word r_w_con.v(131) " "Warning: Verilog HDL Always Construct warning at r_w_con.v(131): variable \"con_word\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"con_word\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 131 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "a_mode_io r_w_con.v(138) " "Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable \"a_mode_io\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"a_mode_io\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "b_mode_io r_w_con.v(138) " "Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable \"b_mode_io\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"b_mode_io\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_upper_io r_w_con.v(138) " "Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable \"c_upper_io\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"c_upper_io\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_lower_io r_w_con.v(138) " "Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable \"c_lower_io\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"c_lower_io\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 138 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_upper_io\$latch " "Warning: Latch c_upper_io\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA con_word\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal con_word\[3\]" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0} { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA PRE rst_n " "Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 140 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_lower_io\$latch " "Warning: Latch c_lower_io\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA con_word\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal con_word\[0\]" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0} { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA PRE rst_n " "Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 140 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[0\] " "Warning: Latch con_word\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[1\] " "Warning: Latch con_word\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[2\] " "Warning: Latch con_word\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[3\] " "Warning: Latch con_word\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[7\] " "Warning: Latch con_word\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "b_mode_io\$latch " "Warning: Latch b_mode_io\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA con_word\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal con_word\[1\]" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0} { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA PRE rst_n " "Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 140 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "a_mode_io\$latch " "Warning: Latch a_mode_io\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA con_word\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal con_word\[4\]" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0} { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA PRE rst_n " "Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 140 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[6\] " "Warning: Latch con_word\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[5\] " "Warning: Latch con_word\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "con_word\[4\] " "Warning: Latch con_word\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR rst_n " "Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n" {  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 39 -1 0 } }  } 0}  } { { "r_w_con.v" "" { Text "F:/cfm/8255-quantus/r_w_con/r_w_con.v" 69 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "58 " "Info: Implemented 58 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "14 " "Info: Implemented 14 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 08 20:54:48 2006 " "Info: Processing ended: Wed Nov 08 20:54:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}