r_w_con.fit.eqn

用Verilog实现8255芯片功能

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--A1L9 is always1~0 at LC1_C28
--operation mode is normal

A1L9 = wr_n & !rd_n;

--A1L01 is always1~8 at LC1_C28
--operation mode is normal

A1L01 = wr_n & !rd_n;


--A1L23 is bus_con~54 at LC5_C24
--operation mode is normal

A1L23 = A1L9 & !a1 & !cs_n & !a0;

--A1L53 is bus_con~57 at LC5_C24
--operation mode is normal

A1L53 = A1L9 & !a1 & !cs_n & !a0;


--A1L33 is bus_con~55 at LC1_C24
--operation mode is normal

A1L33 = A1L9 & a0 & !a1 & !cs_n;

--A1L63 is bus_con~58 at LC1_C24
--operation mode is normal

A1L63 = A1L9 & a0 & !a1 & !cs_n;


--A1L43 is bus_con~56 at LC6_C24
--operation mode is normal

A1L43 = A1L9 & a1 & !cs_n & !a0;

--A1L73 is bus_con~59 at LC6_C24
--operation mode is normal

A1L73 = A1L9 & a1 & !cs_n & !a0;


--A1L24 is c_port~11 at LC2_C24
--operation mode is normal

A1L24 = a1 & !cs_n & !a0;

--A1L34 is c_port~12 at LC2_C24
--operation mode is normal

A1L34 = a1 & !cs_n & !a0;


--A1L05 is c_set_rst~0 at LC6_F18
--operation mode is normal

A1L05 = a1 & a0 & !con_word[7] & !cs_n;

--A1L15 is c_set_rst~10 at LC6_F18
--operation mode is normal

A1L15 = a1 & a0 & !con_word[7] & !cs_n;


--A1L52 is b_port~12 at LC7_C24
--operation mode is normal

A1L52 = a0 & !a1 & !cs_n;

--A1L62 is b_port~13 at LC7_C24
--operation mode is normal

A1L62 = a0 & !a1 & !cs_n;


--A1L7 is a_port~3 at LC3_C24
--operation mode is normal

A1L7 = !a1 & !cs_n & !a0;

--A1L8 is a_port~4 at LC3_C24
--operation mode is normal

A1L8 = !a1 & !cs_n & !a0;


--A1L37 is con~17 at LC2_A24
--operation mode is normal

A1L37 = a1 & a0 & !cs_n;

--A1L47 is con~18 at LC2_A24
--operation mode is normal

A1L47 = a1 & a0 & !cs_n;


--A1L51 is always3~59 at LC3_A2
--operation mode is normal

A1L51 = con_word[0] # con_word[1] # con_word[2] # con_word[3];

--A1L81 is always3~62 at LC3_A2
--operation mode is normal

A1L81 = con_word[0] # con_word[1] # con_word[2] # con_word[3];


--A1L61 is always3~60 at LC3_F18
--operation mode is normal

A1L61 = con_word[7] # con_word[6] # con_word[5] # con_word[4];

--A1L91 is always3~63 at LC3_F18
--operation mode is normal

A1L91 = con_word[7] # con_word[6] # con_word[5] # con_word[4];


--A1L71 is always3~61 at LC2_F18
--operation mode is normal

A1L71 = A1L51 # A1L61 # !rst_n;

--A1L02 is always3~64 at LC2_F18
--operation mode is normal

A1L02 = A1L51 # A1L61 # !rst_n;


--c_upper_io$latch is c_upper_io$latch at LC5_A2
--operation mode is normal

c_upper_io$latch = A1L71 & con_word[3] # !A1L71 & (c_upper_io$latch) # !rst_n;

--A1L45 is c_upper_io$latch~3 at LC5_A2
--operation mode is normal

A1L45 = A1L71 & con_word[3] # !A1L71 & (c_upper_io$latch) # !rst_n;


--c_lower_io$latch is c_lower_io$latch at LC2_A2
--operation mode is normal

c_lower_io$latch = A1L71 & con_word[0] # !A1L71 & (c_lower_io$latch) # !rst_n;

--A1L04 is c_lower_io$latch~3 at LC2_A2
--operation mode is normal

A1L04 = A1L71 & con_word[0] # !A1L71 & (c_lower_io$latch) # !rst_n;


--A1L31 is always2~5 at LC4_C24
--operation mode is normal

A1L31 = a1 & a0 & !cs_n # !rst_n;

--A1L41 is always2~20 at LC4_C24
--operation mode is normal

A1L41 = a1 & a0 & !cs_n # !rst_n;


--con_word[0] is con_word[0] at LC4_A2
--operation mode is normal

con_word[0] = rst_n & (A1L31 & d_inbuf[0] # !A1L31 & (con_word[0]));

--A1L85 is con_word[0]~80 at LC4_A2
--operation mode is normal

A1L85 = rst_n & (A1L31 & d_inbuf[0] # !A1L31 & (con_word[0]));


--con_word[1] is con_word[1] at LC1_A2
--operation mode is normal

con_word[1] = rst_n & (A1L31 & d_inbuf[1] # !A1L31 & (con_word[1]));

--A1L06 is con_word[1]~81 at LC1_A2
--operation mode is normal

A1L06 = rst_n & (A1L31 & d_inbuf[1] # !A1L31 & (con_word[1]));


--con_word[2] is con_word[2] at LC8_A18
--operation mode is normal

con_word[2] = rst_n & (A1L31 & d_inbuf[2] # !A1L31 & (con_word[2]));

--A1L26 is con_word[2]~82 at LC8_A18
--operation mode is normal

A1L26 = rst_n & (A1L31 & d_inbuf[2] # !A1L31 & (con_word[2]));


--con_word[3] is con_word[3] at LC6_A2
--operation mode is normal

con_word[3] = rst_n & (A1L31 & d_inbuf[3] # !A1L31 & (con_word[3]));

--A1L46 is con_word[3]~83 at LC6_A2
--operation mode is normal

A1L46 = rst_n & (A1L31 & d_inbuf[3] # !A1L31 & (con_word[3]));


--con_word[7] is con_word[7] at LC4_F18
--operation mode is normal

con_word[7] = rst_n & (A1L31 & d_inbuf[7] # !A1L31 & (con_word[7]));

--A1L27 is con_word[7]~84 at LC4_F18
--operation mode is normal

A1L27 = rst_n & (A1L31 & d_inbuf[7] # !A1L31 & (con_word[7]));


--b_mode_io$latch is b_mode_io$latch at LC8_A2
--operation mode is normal

b_mode_io$latch = A1L71 & con_word[1] # !A1L71 & (b_mode_io$latch) # !rst_n;

--A1L32 is b_mode_io$latch~3 at LC8_A2
--operation mode is normal

A1L32 = A1L71 & con_word[1] # !A1L71 & (b_mode_io$latch) # !rst_n;


--a_mode_io$latch is a_mode_io$latch at LC1_F18
--operation mode is normal

a_mode_io$latch = A1L71 & con_word[4] # !A1L71 & (a_mode_io$latch) # !rst_n;

--A1L5 is a_mode_io$latch~3 at LC1_F18
--operation mode is normal

A1L5 = A1L71 & con_word[4] # !A1L71 & (a_mode_io$latch) # !rst_n;


--con_word[6] is con_word[6] at LC5_F18
--operation mode is normal

con_word[6] = rst_n & (A1L31 & d_inbuf[6] # !A1L31 & (con_word[6]));

--A1L07 is con_word[6]~85 at LC5_F18
--operation mode is normal

A1L07 = rst_n & (A1L31 & d_inbuf[6] # !A1L31 & (con_word[6]));


--con_word[5] is con_word[5] at LC7_F18
--operation mode is normal

con_word[5] = rst_n & (A1L31 & d_inbuf[5] # !A1L31 & (con_word[5]));

--A1L86 is con_word[5]~86 at LC7_F18
--operation mode is normal

A1L86 = rst_n & (A1L31 & d_inbuf[5] # !A1L31 & (con_word[5]));


--con_word[4] is con_word[4] at LC8_F18
--operation mode is normal

con_word[4] = rst_n & (A1L31 & d_inbuf[4] # !A1L31 & (con_word[4]));

--A1L66 is con_word[4]~87 at LC8_F18
--operation mode is normal

A1L66 = rst_n & (A1L31 & d_inbuf[4] # !A1L31 & (con_word[4]));


--wr_n is wr_n at PIN_125
--operation mode is input

wr_n = INPUT();


--rd_n is rd_n at PIN_55
--operation mode is input

rd_n = INPUT();


--a1 is a1 at PIN_124
--operation mode is input

a1 = INPUT();


--cs_n is cs_n at PIN_54
--operation mode is input

cs_n = INPUT();


--a0 is a0 at PIN_56
--operation mode is input

a0 = INPUT();


--rst_n is rst_n at PIN_126
--operation mode is input

rst_n = INPUT();


--d_inbuf[0] is d_inbuf[0] at PIN_68
--operation mode is input

d_inbuf[0] = INPUT();


--d_inbuf[1] is d_inbuf[1] at PIN_113
--operation mode is input

d_inbuf[1] = INPUT();


--d_inbuf[2] is d_inbuf[2] at PIN_8
--operation mode is input

d_inbuf[2] = INPUT();


--d_inbuf[3] is d_inbuf[3] at PIN_102
--operation mode is input

d_inbuf[3] = INPUT();


--d_inbuf[7] is d_inbuf[7] at PIN_32
--operation mode is input

d_inbuf[7] = INPUT();


--d_inbuf[6] is d_inbuf[6] at PIN_31
--operation mode is input

d_inbuf[6] = INPUT();


--d_inbuf[5] is d_inbuf[5] at PIN_78
--operation mode is input

d_inbuf[5] = INPUT();


--d_inbuf[4] is d_inbuf[4] at PIN_81
--operation mode is input

d_inbuf[4] = INPUT();


--lk_bus is lk_bus at PIN_11
--operation mode is output

lk_bus = OUTPUT(A1L9);


--bus_con[0] is bus_con[0] at PIN_48
--operation mode is output

bus_con[0] = OUTPUT(A1L23);


--bus_con[1] is bus_con[1] at PIN_12
--operation mode is output

bus_con[1] = OUTPUT(A1L33);


--bus_con[2] is bus_con[2] at PIN_17
--operation mode is output

bus_con[2] = OUTPUT(A1L43);


--bus_con[3] is bus_con[3] at PIN_95
--operation mode is output

bus_con[3] = OUTPUT(!A1L11);


--r_w is r_w at PIN_133
--operation mode is output

r_w = OUTPUT(!A1L21);


--c_port is c_port at PIN_13
--operation mode is output

c_port = OUTPUT(A1L24);


--c_upper_io is c_upper_io at PIN_109
--operation mode is output

c_upper_io = OUTPUT(c_upper_io$latch);


--c_lower_io is c_lower_io at PIN_73
--operation mode is output

c_lower_io = OUTPUT(c_lower_io$latch);


--c_set_rst[0] is c_set_rst[0] at PIN_80
--operation mode is output

c_set_rst[0] = OUTPUT(con_word[0]);


--c_set_rst[1] is c_set_rst[1] at PIN_110
--operation mode is output

c_set_rst[1] = OUTPUT(con_word[1]);


--c_set_rst[2] is c_set_rst[2] at PIN_7
--operation mode is output

c_set_rst[2] = OUTPUT(con_word[2]);


--c_set_rst[3] is c_set_rst[3] at PIN_101
--operation mode is output

c_set_rst[3] = OUTPUT(con_word[3]);


--c_set_rst[4] is c_set_rst[4] at PIN_79
--operation mode is output

c_set_rst[4] = OUTPUT(A1L05);


--b_mode_io is b_mode_io at PIN_100
--operation mode is output

b_mode_io = OUTPUT(b_mode_io$latch);


--b_port is b_port at PIN_18
--operation mode is output

b_port = OUTPUT(A1L52);


--a_mode_io is a_mode_io at PIN_82
--operation mode is output

a_mode_io = OUTPUT(a_mode_io$latch);


--a_port is a_port at PIN_96
--operation mode is output

a_port = OUTPUT(A1L7);


--con is con at PIN_131
--operation mode is output

con = OUTPUT(A1L37);


--A1L11 is always1~9 at LC8_C22
--operation mode is normal

A1L11 = wr_n & !rd_n;


--A1L21 is always1~10 at LC2_A28
--operation mode is normal

A1L21 = wr_n & !rd_n;