📄 r_w_con.tan.rpt
字号:
; N/A ; None ; 18.200 ns ; cs_n ; c_set_rst[4] ;
; N/A ; None ; 18.200 ns ; a0 ; c_set_rst[4] ;
; N/A ; None ; 18.000 ns ; rst_n ; c_set_rst[4] ;
; N/A ; None ; 17.300 ns ; d_inbuf[0] ; c_set_rst[0] ;
; N/A ; None ; 17.100 ns ; d_inbuf[2] ; c_set_rst[2] ;
; N/A ; None ; 17.100 ns ; a1 ; c_set_rst[0] ;
; N/A ; None ; 17.000 ns ; cs_n ; c_set_rst[0] ;
; N/A ; None ; 17.000 ns ; a0 ; c_set_rst[0] ;
; N/A ; None ; 16.800 ns ; rst_n ; c_set_rst[0] ;
; N/A ; None ; 16.700 ns ; a1 ; c_set_rst[2] ;
; N/A ; None ; 16.600 ns ; cs_n ; c_set_rst[2] ;
; N/A ; None ; 16.600 ns ; a0 ; c_set_rst[2] ;
; N/A ; None ; 16.400 ns ; rst_n ; c_set_rst[2] ;
; N/A ; None ; 16.200 ns ; a1 ; c_set_rst[3] ;
; N/A ; None ; 16.100 ns ; cs_n ; c_set_rst[3] ;
; N/A ; None ; 16.100 ns ; a0 ; c_set_rst[3] ;
; N/A ; None ; 15.900 ns ; rst_n ; c_set_rst[3] ;
; N/A ; None ; 15.700 ns ; a1 ; c_set_rst[1] ;
; N/A ; None ; 15.700 ns ; d_inbuf[1] ; c_set_rst[1] ;
; N/A ; None ; 15.600 ns ; cs_n ; c_set_rst[1] ;
; N/A ; None ; 15.600 ns ; a0 ; c_set_rst[1] ;
; N/A ; None ; 15.400 ns ; rst_n ; c_set_rst[1] ;
; N/A ; None ; 15.200 ns ; d_inbuf[3] ; c_set_rst[3] ;
; N/A ; None ; 14.700 ns ; wr_n ; bus_con[1] ;
; N/A ; None ; 14.500 ns ; wr_n ; bus_con[2] ;
; N/A ; None ; 14.500 ns ; rd_n ; bus_con[1] ;
; N/A ; None ; 14.300 ns ; rd_n ; bus_con[2] ;
; N/A ; None ; 14.100 ns ; wr_n ; bus_con[0] ;
; N/A ; None ; 13.900 ns ; rd_n ; bus_con[0] ;
; N/A ; None ; 12.300 ns ; a1 ; a_port ;
; N/A ; None ; 12.300 ns ; cs_n ; a_port ;
; N/A ; None ; 12.300 ns ; wr_n ; bus_con[3] ;
; N/A ; None ; 12.100 ns ; a0 ; a_port ;
; N/A ; None ; 12.100 ns ; rd_n ; bus_con[3] ;
; N/A ; None ; 11.800 ns ; a1 ; b_port ;
; N/A ; None ; 11.800 ns ; a0 ; b_port ;
; N/A ; None ; 11.800 ns ; a1 ; c_port ;
; N/A ; None ; 11.800 ns ; cs_n ; c_port ;
; N/A ; None ; 11.800 ns ; a1 ; bus_con[1] ;
; N/A ; None ; 11.800 ns ; a0 ; bus_con[1] ;
; N/A ; None ; 11.600 ns ; cs_n ; b_port ;
; N/A ; None ; 11.600 ns ; a0 ; c_port ;
; N/A ; None ; 11.600 ns ; a1 ; bus_con[2] ;
; N/A ; None ; 11.600 ns ; cs_n ; bus_con[2] ;
; N/A ; None ; 11.600 ns ; cs_n ; bus_con[1] ;
; N/A ; None ; 11.600 ns ; wr_n ; lk_bus ;
; N/A ; None ; 11.400 ns ; a0 ; bus_con[2] ;
; N/A ; None ; 11.400 ns ; rd_n ; lk_bus ;
; N/A ; None ; 11.200 ns ; a1 ; bus_con[0] ;
; N/A ; None ; 11.200 ns ; cs_n ; bus_con[0] ;
; N/A ; None ; 11.100 ns ; a1 ; con ;
; N/A ; None ; 11.100 ns ; a0 ; con ;
; N/A ; None ; 11.000 ns ; wr_n ; r_w ;
; N/A ; None ; 11.000 ns ; a0 ; bus_con[0] ;
; N/A ; None ; 10.900 ns ; cs_n ; con ;
; N/A ; None ; 10.800 ns ; rd_n ; r_w ;
+-------+-------------------+-----------------+------------+--------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Nov 08 20:54:59 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off r_w_con -c r_w_con
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis found one or more latches implemented as combinational loops
Warning: Node "con_word[7]" is a latch
Warning: Node "con_word[0]" is a latch
Warning: Node "con_word[1]" is a latch
Warning: Node "con_word[2]" is a latch
Warning: Node "con_word[3]" is a latch
Warning: Node "con_word[6]" is a latch
Warning: Node "con_word[5]" is a latch
Warning: Node "con_word[4]" is a latch
Warning: Node "c_upper_io$latch" is a latch
Warning: Node "c_lower_io$latch" is a latch
Warning: Node "b_mode_io$latch" is a latch
Warning: Node "a_mode_io$latch" is a latch
Info: Found combinational loop of 1 nodes
Info: Node "a_mode_io$latch"
Info: Found combinational loop of 1 nodes
Info: Node "b_mode_io$latch"
Info: Found combinational loop of 1 nodes
Info: Node "c_lower_io$latch"
Info: Found combinational loop of 1 nodes
Info: Node "c_upper_io$latch"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[4]"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[5]"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[6]"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[3]"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[2]"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[1]"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[0]"
Info: Found combinational loop of 1 nodes
Info: Node "con_word[7]"
Info: Longest tpd from source pin "d_inbuf[2]" to destination pin "b_mode_io" is 27.400 ns
Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 2; PIN Node = 'd_inbuf[2]'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 8.900 ns; Loc. = LC8_A18; Fanout = 3; COMB LOOP Node = 'con_word[2]'
Info: Loc. = LC8_A18; Node "con_word[2]"
Info: 3: + IC(1.300 ns) + CELL(1.600 ns) = 11.800 ns; Loc. = LC3_A2; Fanout = 1; COMB Node = 'always3~59'
Info: 4: + IC(2.700 ns) + CELL(1.600 ns) = 16.100 ns; Loc. = LC2_F18; Fanout = 8; COMB Node = 'always3~61'
Info: 5: + IC(0.000 ns) + CELL(4.100 ns) = 20.200 ns; Loc. = LC8_A2; Fanout = 2; COMB LOOP Node = 'b_mode_io$latch'
Info: Loc. = LC1_A2; Node "con_word[1]"
Info: Loc. = LC8_A2; Node "b_mode_io$latch"
Info: 6: + IC(0.900 ns) + CELL(6.300 ns) = 27.400 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'b_mode_io'
Info: Total cell delay = 22.500 ns ( 82.12 % )
Info: Total interconnect delay = 4.900 ns ( 17.88 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 13 warnings
Info: Processing ended: Wed Nov 08 20:55:00 2006
Info: Elapsed time: 00:00:02
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