r_w_con.map.rpt

用Verilog实现8255芯片功能

;     -- Total 2-input functions  ; 1         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 0         ;
; I/O pins                        ; 33        ;
; Maximum fan-out node            ; rst_n     ;
; Maximum fan-out                 ; 14        ;
; Total fan-out                   ; 112       ;
; Average fan-out                 ; 1.93      ;
+---------------------------------+-----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; |r_w_con                   ; 25 (25)     ; 0            ; 0           ; 33   ; 25 (25)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |r_w_con            ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; c_upper_io$latch                              ;    ;
; c_lower_io$latch                              ;    ;
; con_word[0]                                   ;    ;
; con_word[1]                                   ;    ;
; con_word[2]                                   ;    ;
; con_word[3]                                   ;    ;
; con_word[7]                                   ;    ;
; b_mode_io$latch                               ;    ;
; a_mode_io$latch                               ;    ;
; con_word[6]                                   ;    ;
; con_word[5]                                   ;    ;
; con_word[4]                                   ;    ;
; Number of user-specified and inferred latches ; 12 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/cfm/8255-quantus/r_w_con/r_w_con.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Nov 08 20:54:48 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off r_w_con -c r_w_con
Info: Found 1 design units, including 1 entities, in source file r_w_con.v
    Info: Found entity 1: r_w_con
Info: Elaborating entity "r_w_con" for the top level hierarchy
Warning: Verilog HDL Always Construct warning at r_w_con.v(131): variable "con_word" may not be assigned a new value in every possible path through the Always Construct.  Variable "con_word" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable "a_mode_io" may not be assigned a new value in every possible path through the Always Construct.  Variable "a_mode_io" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable "b_mode_io" may not be assigned a new value in every possible path through the Always Construct.  Variable "b_mode_io" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable "c_upper_io" may not be assigned a new value in every possible path through the Always Construct.  Variable "c_upper_io" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at r_w_con.v(138): variable "c_lower_io" may not be assigned a new value in every possible path through the Always Construct.  Variable "c_lower_io" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Latch c_upper_io$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal con_word[3]
    Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n
Warning: Latch c_lower_io$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal con_word[0]
    Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n
Warning: Latch con_word[0] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Warning: Latch con_word[1] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Warning: Latch con_word[2] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Warning: Latch con_word[3] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Warning: Latch con_word[7] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Warning: Latch b_mode_io$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal con_word[1]
    Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n
Warning: Latch a_mode_io$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal con_word[4]
    Warning: Ports ENA and PRE on the latch are fed by the same signal rst_n
Warning: Latch con_word[6] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Warning: Latch con_word[5] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Warning: Latch con_word[4] has unsafe behavior
    Warning: Ports ENA and CLR on the latch are fed by the same signal rst_n
Info: Implemented 58 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 19 output pins
    Info: Implemented 25 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings
    Info: Processing ended: Wed Nov 08 20:54:48 2006
    Info: Elapsed time: 00:00:01