data_bus_buf.map.qmsg

用Verilog实现8255芯片功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 08 18:39:51 2006 " "Info: Processing started: Wed Nov 08 18:39:51 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off data_bus_buf -c data_bus_buf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_bus_buf -c data_bus_buf" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_bus_buf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_bus_buf.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_bus_buf " "Info: Found entity 1: data_bus_buf" {  } { { "data_bus_buf.v" "" { Text "F:/cfm/8255-quantus/data_bus_buf/data_bus_buf.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "data_bus_buf " "Info: Elaborating entity \"data_bus_buf\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "d_inbuf data_bus_buf.v(32) " "Warning: Verilog HDL Always Construct warning at data_bus_buf.v(32): variable \"d_inbuf\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"d_inbuf\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "data_bus_buf.v" "" { Text "F:/cfm/8255-quantus/data_bus_buf/data_bus_buf.v" 32 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 08 18:39:52 2006 " "Info: Processing ended: Wed Nov 08 18:39:52 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}