data_bus_buf.v

来自「用Verilog实现8255芯片功能」· Verilog 代码 · 共 33 行

//////////////////////////////////////////////////
//         the data bus buffer of 8255          //
//model name:    data_bus_buf                   //
//time:           2006.10.28                    //
//author:        cheng fangmin                  //
//function:  transfer the data between CPU and  //
//         internal bus                         //
//////////////////////////////////////////////////
module data_bus_buf(//input
                    lk_bus,
                    d_outbuf,
                    //output
                    d_inbuf,
                    //inout
                    data_bus
                    );
//control signal
   input lk_bus;
//data come from internal bus
   input[7:0] d_outbuf;
//data go to internal bus   
   output[7:0] d_inbuf;
//connect with CPU data bus
   inout[7:0] data_bus;

   reg[7:0] d_inbuf;
//when lk_bus=1,data go to the CPU data bus
assign  data_bus=(lk_bus)? d_outbuf:8'hzz;
always  @(lk_bus or data_bus)
        begin
          if(!lk_bus)  d_inbuf=data_bus;
        end
endmodule