📄 data_bus_buf.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--d_inbuf[0]$latch is d_inbuf[0]$latch
--operation mode is normal
d_inbuf[0]$latch = lk_bus & (d_inbuf[0]$latch) # !lk_bus & A1L73;
--A1L4 is d_inbuf[0]$latch~3
--operation mode is normal
A1L4 = lk_bus & (d_inbuf[0]$latch) # !lk_bus & A1L73;
--d_inbuf[1]$latch is d_inbuf[1]$latch
--operation mode is normal
d_inbuf[1]$latch = lk_bus & (d_inbuf[1]$latch) # !lk_bus & A1L93;
--A1L7 is d_inbuf[1]$latch~3
--operation mode is normal
A1L7 = lk_bus & (d_inbuf[1]$latch) # !lk_bus & A1L93;
--d_inbuf[2]$latch is d_inbuf[2]$latch
--operation mode is normal
d_inbuf[2]$latch = lk_bus & (d_inbuf[2]$latch) # !lk_bus & A1L14;
--A1L01 is d_inbuf[2]$latch~3
--operation mode is normal
A1L01 = lk_bus & (d_inbuf[2]$latch) # !lk_bus & A1L14;
--d_inbuf[3]$latch is d_inbuf[3]$latch
--operation mode is normal
d_inbuf[3]$latch = lk_bus & (d_inbuf[3]$latch) # !lk_bus & A1L34;
--A1L31 is d_inbuf[3]$latch~3
--operation mode is normal
A1L31 = lk_bus & (d_inbuf[3]$latch) # !lk_bus & A1L34;
--d_inbuf[4]$latch is d_inbuf[4]$latch
--operation mode is normal
d_inbuf[4]$latch = lk_bus & (d_inbuf[4]$latch) # !lk_bus & A1L54;
--A1L61 is d_inbuf[4]$latch~3
--operation mode is normal
A1L61 = lk_bus & (d_inbuf[4]$latch) # !lk_bus & A1L54;
--d_inbuf[5]$latch is d_inbuf[5]$latch
--operation mode is normal
d_inbuf[5]$latch = lk_bus & (d_inbuf[5]$latch) # !lk_bus & A1L74;
--A1L91 is d_inbuf[5]$latch~3
--operation mode is normal
A1L91 = lk_bus & (d_inbuf[5]$latch) # !lk_bus & A1L74;
--d_inbuf[6]$latch is d_inbuf[6]$latch
--operation mode is normal
d_inbuf[6]$latch = lk_bus & (d_inbuf[6]$latch) # !lk_bus & A1L94;
--A1L22 is d_inbuf[6]$latch~3
--operation mode is normal
A1L22 = lk_bus & (d_inbuf[6]$latch) # !lk_bus & A1L94;
--d_inbuf[7]$latch is d_inbuf[7]$latch
--operation mode is normal
d_inbuf[7]$latch = lk_bus & (d_inbuf[7]$latch) # !lk_bus & A1L15;
--A1L52 is d_inbuf[7]$latch~3
--operation mode is normal
A1L52 = lk_bus & (d_inbuf[7]$latch) # !lk_bus & A1L15;
--lk_bus is lk_bus
--operation mode is input
lk_bus = INPUT();
--d_outbuf[0] is d_outbuf[0]
--operation mode is input
d_outbuf[0] = INPUT();
--d_outbuf[1] is d_outbuf[1]
--operation mode is input
d_outbuf[1] = INPUT();
--d_outbuf[2] is d_outbuf[2]
--operation mode is input
d_outbuf[2] = INPUT();
--d_outbuf[3] is d_outbuf[3]
--operation mode is input
d_outbuf[3] = INPUT();
--d_outbuf[4] is d_outbuf[4]
--operation mode is input
d_outbuf[4] = INPUT();
--d_outbuf[5] is d_outbuf[5]
--operation mode is input
d_outbuf[5] = INPUT();
--d_outbuf[6] is d_outbuf[6]
--operation mode is input
d_outbuf[6] = INPUT();
--d_outbuf[7] is d_outbuf[7]
--operation mode is input
d_outbuf[7] = INPUT();
--d_inbuf[0] is d_inbuf[0]
--operation mode is output
d_inbuf[0] = OUTPUT(d_inbuf[0]$latch);
--d_inbuf[1] is d_inbuf[1]
--operation mode is output
d_inbuf[1] = OUTPUT(d_inbuf[1]$latch);
--d_inbuf[2] is d_inbuf[2]
--operation mode is output
d_inbuf[2] = OUTPUT(d_inbuf[2]$latch);
--d_inbuf[3] is d_inbuf[3]
--operation mode is output
d_inbuf[3] = OUTPUT(d_inbuf[3]$latch);
--d_inbuf[4] is d_inbuf[4]
--operation mode is output
d_inbuf[4] = OUTPUT(d_inbuf[4]$latch);
--d_inbuf[5] is d_inbuf[5]
--operation mode is output
d_inbuf[5] = OUTPUT(d_inbuf[5]$latch);
--d_inbuf[6] is d_inbuf[6]
--operation mode is output
d_inbuf[6] = OUTPUT(d_inbuf[6]$latch);
--d_inbuf[7] is d_inbuf[7]
--operation mode is output
d_inbuf[7] = OUTPUT(d_inbuf[7]$latch);
--A1L73 is data_bus[0]~7
--operation mode is bidir
A1L73 = data_bus[0];
--data_bus[0] is data_bus[0]
--operation mode is bidir
data_bus[0]_tri_out = TRI(d_outbuf[0], lk_bus);
data_bus[0] = BIDIR(data_bus[0]_tri_out);
--A1L93 is data_bus[1]~6
--operation mode is bidir
A1L93 = data_bus[1];
--data_bus[1] is data_bus[1]
--operation mode is bidir
data_bus[1]_tri_out = TRI(d_outbuf[1], lk_bus);
data_bus[1] = BIDIR(data_bus[1]_tri_out);
--A1L14 is data_bus[2]~5
--operation mode is bidir
A1L14 = data_bus[2];
--data_bus[2] is data_bus[2]
--operation mode is bidir
data_bus[2]_tri_out = TRI(d_outbuf[2], lk_bus);
data_bus[2] = BIDIR(data_bus[2]_tri_out);
--A1L34 is data_bus[3]~4
--operation mode is bidir
A1L34 = data_bus[3];
--data_bus[3] is data_bus[3]
--operation mode is bidir
data_bus[3]_tri_out = TRI(d_outbuf[3], lk_bus);
data_bus[3] = BIDIR(data_bus[3]_tri_out);
--A1L54 is data_bus[4]~3
--operation mode is bidir
A1L54 = data_bus[4];
--data_bus[4] is data_bus[4]
--operation mode is bidir
data_bus[4]_tri_out = TRI(d_outbuf[4], lk_bus);
data_bus[4] = BIDIR(data_bus[4]_tri_out);
--A1L74 is data_bus[5]~2
--operation mode is bidir
A1L74 = data_bus[5];
--data_bus[5] is data_bus[5]
--operation mode is bidir
data_bus[5]_tri_out = TRI(d_outbuf[5], lk_bus);
data_bus[5] = BIDIR(data_bus[5]_tri_out);
--A1L94 is data_bus[6]~1
--operation mode is bidir
A1L94 = data_bus[6];
--data_bus[6] is data_bus[6]
--operation mode is bidir
data_bus[6]_tri_out = TRI(d_outbuf[6], lk_bus);
data_bus[6] = BIDIR(data_bus[6]_tri_out);
--A1L15 is data_bus[7]~0
--operation mode is bidir
A1L15 = data_bus[7];
--data_bus[7] is data_bus[7]
--operation mode is bidir
data_bus[7]_tri_out = TRI(d_outbuf[7], lk_bus);
data_bus[7] = BIDIR(data_bus[7]_tri_out);
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