top_8255.v

用Verilog实现8255芯片功能

//////////////////////////////////////////////
//         8255A的顶层模块top_8255.v        //
//             2006.11. 6                   //
//          cheng fangmin                   //
//function: 8255最上层的模块，将其他子模块  //
//         连接起来                         //
//////////////////////////////////////////////
module top_8255(//input control signal
                rst_n,
                cs_n,
                a1,
                a0,
                wr_n,
                rd_n,
                //data bus
                data_bus,
                a_bus,
                b_bus,
                c_bus
                );
input rst_n,cs_n,a1,a0,wr_n,rd_n;
inout[7:0] data_bus,a_bus,b_bus,c_bus;

//internal wire
  wire[7:0] d_outbuf,d_inbuf;
  wire[7:0] a_outbuf,a_inbuf;
  wire[7:0] b_outbuf,b_inbuf;
  wire[7:0] c_outbuf,c_inbuf;
  
  //control signal
  wire lk_bus;
  
  wire[3:0] bus_con;
  
  wire a_mode_io,a_port;
  
  wire b_mode_io,b_port;
  
  wire c_port,r_w,c_upper_io,c_lower_io;
  wire[4:0] c_set_rst;
  
  //link module
  data_bus_buf data_buf1(//input
                        .lk_bus(lk_bus),
                        .d_outbuf(d_outbuf),
                        //output
                        .d_inbuf(d_inbuf),
                        //inout
                        .data_bus(data_bus)
                        );
  inter_bus inter_bus1(.bus_con(bus_con),
                       //connect data bus buffer
                       .d_inbuf(d_inbuf),
                       .d_outbuf(d_outbuf),
                       // connect A port
                       .a_outbuf(a_outbuf),
                       .a_inbuf(a_inbuf),
                       // connect b port
                       .b_outbuf(b_outbuf),
                       .b_inbuf(b_inbuf),
                       // connect c port
                       .c_outbuf(c_outbuf),
                       .c_inbuf(c_inbuf)
                       );
   r_w_con r_w_con1(//input
                   .rst_n(rst_n),  //reset signal
                   .cs_n(cs_n),   //chip select
                   .a0(a0),     
                   .a1(a1),
                   .wr_n(wr_n),   //write signal
                   .rd_n(rd_n),   //read signal
                   // data input
                   .d_inbuf(d_inbuf),
                   //output
                   //control data bus buffer
                   .lk_bus(lk_bus),
                   //control internal bus
                   .bus_con(bus_con),
                   //control C port
               		 .r_w(r_w),
                   .c_port(c_port),
                   .c_upper_io(c_upper_io),
                   .c_lower_io(c_lower_io),
                   .c_set_rst(c_set_rst),
                   //control B port
                   .b_mode_io(b_mode_io),
                   .b_port(b_port),
                   //control A port
                  .a_mode_io(a_mode_io),//A口在模式0下是输入还是输出   
                  .a_port(a_port)    //为1，选中对A口操作。
                  );
  aa_port aa_port1(//input
                  .a_port(a_port),
                  .a_mode_io(a_mode_io),
                  .a_outbuf(a_outbuf),
                  //output
                  .a_inbuf(a_inbuf),
                  //inout
                  .a_bus(a_bus)
                  );
 bb_port bb_port1(//input
               .b_port(b_port),
               .b_mode_io(b_mode_io),
               .b_outbuf(b_outbuf),
               //output
               .b_inbuf(b_inbuf),
               //inout
               .b_bus(b_bus)
               );
cc_port cc_port1(//input
                .rst_n(rst_n),
                .c_port(c_port),
                .r_w(r_w),
                .c_upper_io(c_upper_io),
                .c_lower_io(c_lower_io),
                .c_set_rst(c_set_rst),
                .c_outbuf(c_outbuf),
                //output
                .c_inbuf(c_inbuf),
                //inout
                .c_bus(c_bus)
                );
 endmodule

//////////////////////////////////////////////////
//         the data bus buffer of 8255          //
//model name:     inter_bus                     //
//time:           2006.10.28                    //
//author:       cheng fangmin                   //
//function:   在数据总线缓冲器和A口             //
//           （或B口或C口）之间建立数据传输通道 //
//////////////////////////////////////////////////
module inter_bus(bus_con,
                 //connect data bus buffer
                 d_inbuf,
                 d_outbuf,
                 // connect A port
                 a_outbuf,
                 a_inbuf,
                 // connect b port
                 b_outbuf,
                 b_inbuf,
                 // connect c port
                 c_outbuf,
                 c_inbuf);
//control signal  
input[3:0] bus_con;
wire d_link,a_link,b_link,c_link;


input[7:0]    d_inbuf,  a_inbuf,  b_inbuf,  c_inbuf;
output[7:0]   d_outbuf, a_outbuf, b_outbuf, c_outbuf;
wire[7:0]     bus;
assign {d_link,c_link,b_link,a_link}=bus_con;

data_bus_buf  d_bus1(//input
                    .lk_bus(d_link),
                    .d_outbuf(d_inbuf),
                    //output
                    .d_inbuf(d_outbuf),
                    //inout
                    .data_bus(bus)
                    );
data_bus_buf  a_bus1(//input
                    .lk_bus(a_link),
                    .d_outbuf(a_inbuf),
                    //output
                    .d_inbuf(a_outbuf),
                    //inout
                    .data_bus(bus)
                    );
data_bus_buf  b_bus1(//input
                    .lk_bus(b_link),
                    .d_outbuf(b_inbuf),
                    //output
                    .d_inbuf(b_outbuf),
                    //inout
                    .data_bus(bus)
                    );
data_bus_buf  c_bus1(//input
                    .lk_bus(c_link),
                    .d_outbuf(c_inbuf),
                    //output
                    .d_inbuf(c_outbuf),
                    //inout
                    .data_bus(bus)
                    );
endmodule


//////////////////////////////////////////////////
//         the data bus buffer of 8255          //
//model name:    data_bus_buf                   //
//time:           2006.10.28                    //
//author:        cheng fangmin                  //
//function:  transfer the data between CPU and  //
//         internal bus                         //
//////////////////////////////////////////////////
module data_bus_buf(//input
                    lk_bus,
                    d_outbuf,
                    //output
                    d_inbuf,
                    //inout
                    data_bus
                    );
//control signal
   input lk_bus;
//data come from internal bus
   input[7:0] d_outbuf;
//data go to internal bus   
   output[7:0] d_inbuf;
//connect with CPU data bus
   inout[7:0] data_bus;

   reg[7:0] d_inbuf;
//when lk_bus=1,data go to the CPU data bus
assign  data_bus=(lk_bus)? d_outbuf:8'hzz;
always 
        begin
          if(!lk_bus)  d_inbuf=data_bus;
        end
endmodule

//////////////////////////////////////////////////
//            8255的读写控制逻辑单元            //
//model name:     r_w_con                       //
//time:           2006.10.28                    //
//author:       cheng fangmin                   //
//function:       控制8255                      //
//////////////////////////////////////////////////
module r_w_con(//input
               rst_n,  //reset signal
               cs_n,   //chip select
               a0,     
               a1,
               wr_n,   //write signal
               rd_n,   //read signal
               // data input
               d_inbuf,
               
               //output
                 //control data bus buffer
               lk_bus,
                 //control internal bus
               bus_con,
                 //control C port
               r_w,
               c_port,
               c_upper_io,
               c_lower_io,
               c_set_rst,
                 //control B port
               b_mode_io,
               b_port,
                 //control A port
               a_mode_io,//A口在模式0下是输入还是输出   
               a_port    //为1，选中对A口操作。
               );
//  input from CPU
input rst_n,cs_n,a0,a1,wr_n,rd_n;

//input from data bus buffer
input[7:0] d_inbuf;

//control data bus buffer
output lk_bus;
wire lk_bus;

//control internal bus
output[3:0] bus_con;
reg[3:0] bus_con;

//control A port
output  a_mode_io,a_port;
reg a_mode_io,a_port;

//control B port
output b_mode_io,b_port;
reg b_mode_io,b_port;

//control C port
output c_upper_io,c_lower_io,c_port,r_w;
output[4:0] c_set_rst;
reg c_upper_io,c_lower_io,c_port,r_w;
wire[4:0] c_set_rst;