top_8255.map.qmsg

用Verilog实现8255芯片功能

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[1\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[0\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cc_port cc_port:cc_port1 " "Info: Elaborating entity \"cc_port\" for hierarchy \"cc_port:cc_port1\"" {  } { { "top_8255.v" "cc_port1" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 122 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_inbuf top_8255.v(521) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(521): inferring latch(es) for variable \"c_inbuf\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 521 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[3\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[2\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[1\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[0\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_inbuf top_8255.v(531) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(531): inferring latch(es) for variable \"c_inbuf\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 531 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[7\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[6\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[5\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[4\] top_8255.v(511) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for \"c_inbuf\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 511 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out top_8255.v(549) " "Warning (10235): Verilog HDL Always Construct warning at top_8255.v(549): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 549 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out top_8255.v(551) " "Warning (10235): Verilog HDL Always Construct warning at top_8255.v(551): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 551 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_out top_8255.v(540) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(540): inferring latch(es) for variable \"c_out\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 540 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[7\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[6\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[5\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[4\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[3\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[2\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[1\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[0\] top_8255.v(546) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for \"c_out\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~24 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~24\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~28 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~28\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~32 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~32\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~36 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~36\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~40 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~40\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~44 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~44\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~48 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~48\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~52 " "Warning: Converting TRI node \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~52\" that feeds logic to an OR gate" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to an OR gate" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "cc_port:cc_port1\|c_out\[0\] " "Warning: Latch cc_port:cc_port1\|c_out\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA r_w_con:r_w_con1\|c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1\|c_set_rst\[4\]" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 284 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "cc_port:cc_port1\|c_out\[1\] " "Warning: Latch cc_port:cc_port1\|c_out\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA r_w_con:r_w_con1\|c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1\|c_set_rst\[4\]" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 284 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "cc_port:cc_port1\|c_out\[2\] " "Warning: Latch cc_port:cc_port1\|c_out\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA r_w_con:r_w_con1\|c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1\|c_set_rst\[4\]" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 284 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 546 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}