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📄 top_8255.map.qmsg

📁 用Verilog实现8255芯片功能
💻 QMSG
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{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "a_inbuf top_8255.v(441) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(441): inferring latch(es) for variable \"a_inbuf\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 441 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[7\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[6\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[5\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[4\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[3\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[2\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[1\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_inbuf\[0\] top_8255.v(421) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for \"a_inbuf\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 421 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "a_out top_8255.v(441) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(441): inferring latch(es) for variable \"a_out\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 441 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[7\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[6\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[5\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[4\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[3\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[2\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[1\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_out\[0\] top_8255.v(435) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for \"a_out\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 435 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bb_port bb_port:bb_port1 " "Info: Elaborating entity \"bb_port\" for hierarchy \"bb_port:bb_port1\"" {  } { { "top_8255.v" "bb_port1" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 109 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "b_inbuf top_8255.v(484) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(484): inferring latch(es) for variable \"b_inbuf\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 484 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[7\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[6\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[5\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[4\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[3\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[2\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[1\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_inbuf\[0\] top_8255.v(465) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for \"b_inbuf\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "b_out top_8255.v(484) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(484): inferring latch(es) for variable \"b_out\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 484 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[7\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[6\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[5\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[4\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[3\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_out\[2\] top_8255.v(478) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for \"b_out\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 478 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
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