top_8255.map.qmsg

用Verilog实现8255芯片功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 09 19:18:49 2006 " "Info: Processing started: Thu Nov 09 19:18:49 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top_8255 -c top_8255 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top_8255 -c top_8255" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_8255.v 7 7 " "Info: Found 7 design units, including 7 entities, in source file top_8255.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_8255 " "Info: Found entity 1: top_8255" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 inter_bus " "Info: Found entity 2: inter_bus" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 133 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 data_bus_buf " "Info: Found entity 3: data_bus_buf" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 199 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 r_w_con " "Info: Found entity 4: r_w_con" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 232 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 aa_port " "Info: Found entity 5: aa_port" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 407 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 bb_port " "Info: Found entity 6: bb_port" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 451 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 cc_port " "Info: Found entity 7: cc_port" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 494 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top_8255 " "Info: Elaborating entity \"top_8255\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_bus_buf data_bus_buf:data_buf1 " "Info: Elaborating entity \"data_bus_buf\" for hierarchy \"data_bus_buf:data_buf1\"" {  } { { "top_8255.v" "data_buf1" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 50 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "d_inbuf top_8255.v(222) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(222): inferring latch(es) for variable \"d_inbuf\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 222 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[7\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[6\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[5\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[4\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[3\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[2\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[1\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "d_inbuf\[0\] top_8255.v(221) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for \"d_inbuf\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "inter_bus inter_bus:inter_bus1 " "Info: Elaborating entity \"inter_bus\" for hierarchy \"inter_bus:inter_bus1\"" {  } { { "top_8255.v" "inter_bus1" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 64 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "r_w_con r_w_con:r_w_con1 " "Info: Elaborating entity \"r_w_con\" for hierarchy \"r_w_con:r_w_con1\"" {  } { { "top_8255.v" "r_w_con1" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 91 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "con_word top_8255.v(357) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(357): inferring latch(es) for variable \"con_word\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 357 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[7\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[7\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[6\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[6\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[5\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[5\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[4\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[4\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[3\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[3\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[2\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[2\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[1\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[1\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "con_word\[0\] top_8255.v(291) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for \"con_word\[0\]\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "a_mode_io top_8255.v(364) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(364): inferring latch(es) for variable \"a_mode_io\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 364 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "a_mode_io top_8255.v(275) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(275): inferred latch for \"a_mode_io\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 275 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "b_mode_io top_8255.v(371) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(371): inferring latch(es) for variable \"b_mode_io\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 371 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b_mode_io top_8255.v(279) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(279): inferred latch for \"b_mode_io\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 279 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_upper_io top_8255.v(387) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(387): inferring latch(es) for variable \"c_upper_io\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 387 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_upper_io top_8255.v(283) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(283): inferred latch for \"c_upper_io\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 283 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_lower_io top_8255.v(387) " "Warning (10240): Verilog HDL Always Construct warning at top_8255.v(387): inferring latch(es) for variable \"c_lower_io\", which holds its previous value in one or more paths through the always construct" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 387 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_lower_io top_8255.v(283) " "Info (10041): Verilog HDL or VHDL info at top_8255.v(283): inferred latch for \"c_lower_io\"" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 283 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "aa_port aa_port:aa_port1 " "Info: Elaborating entity \"aa_port\" for hierarchy \"aa_port:aa_port1\"" {  } { { "top_8255.v" "aa_port1" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 100 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}