top_8255.hier_info

用Verilog实现8255芯片功能

|top_8255
rst_n => rst_n~0.IN2
cs_n => cs_n~0.IN1
a1 => a1~0.IN1
a0 => a0~0.IN1
wr_n => wr_n~0.IN1
rd_n => rd_n~0.IN1
data_bus[0] <= data_bus_buf:data_buf1.data_bus
data_bus[1] <= data_bus_buf:data_buf1.data_bus
data_bus[2] <= data_bus_buf:data_buf1.data_bus
data_bus[3] <= data_bus_buf:data_buf1.data_bus
data_bus[4] <= data_bus_buf:data_buf1.data_bus
data_bus[5] <= data_bus_buf:data_buf1.data_bus
data_bus[6] <= data_bus_buf:data_buf1.data_bus
data_bus[7] <= data_bus_buf:data_buf1.data_bus
a_bus[0] <= aa_port:aa_port1.a_bus
a_bus[1] <= aa_port:aa_port1.a_bus
a_bus[2] <= aa_port:aa_port1.a_bus
a_bus[3] <= aa_port:aa_port1.a_bus
a_bus[4] <= aa_port:aa_port1.a_bus
a_bus[5] <= aa_port:aa_port1.a_bus
a_bus[6] <= aa_port:aa_port1.a_bus
a_bus[7] <= aa_port:aa_port1.a_bus
b_bus[0] <= bb_port:bb_port1.b_bus
b_bus[1] <= bb_port:bb_port1.b_bus
b_bus[2] <= bb_port:bb_port1.b_bus
b_bus[3] <= bb_port:bb_port1.b_bus
b_bus[4] <= bb_port:bb_port1.b_bus
b_bus[5] <= bb_port:bb_port1.b_bus
b_bus[6] <= bb_port:bb_port1.b_bus
b_bus[7] <= bb_port:bb_port1.b_bus
c_bus[0] <= cc_port:cc_port1.c_bus
c_bus[1] <= cc_port:cc_port1.c_bus
c_bus[2] <= cc_port:cc_port1.c_bus
c_bus[3] <= cc_port:cc_port1.c_bus
c_bus[4] <= cc_port:cc_port1.c_bus
c_bus[5] <= cc_port:cc_port1.c_bus
c_bus[6] <= cc_port:cc_port1.c_bus
c_bus[7] <= cc_port:cc_port1.c_bus


|top_8255|data_bus_buf:data_buf1
lk_bus => data_bus~8.OE
lk_bus => data_bus~9.OE
lk_bus => data_bus~10.OE
lk_bus => data_bus~11.OE
lk_bus => data_bus~12.OE
lk_bus => data_bus~13.OE
lk_bus => data_bus~14.OE
lk_bus => data_bus~15.OE
lk_bus => d_inbuf[6]$latch.LATCH_ENABLE
lk_bus => d_inbuf[5]$latch.LATCH_ENABLE
lk_bus => d_inbuf[4]$latch.LATCH_ENABLE
lk_bus => d_inbuf[3]$latch.LATCH_ENABLE
lk_bus => d_inbuf[2]$latch.LATCH_ENABLE
lk_bus => d_inbuf[1]$latch.LATCH_ENABLE
lk_bus => d_inbuf[0]$latch.LATCH_ENABLE
lk_bus => d_inbuf[7]$latch.LATCH_ENABLE
d_outbuf[0] => data_bus~15.DATAIN
d_outbuf[1] => data_bus~14.DATAIN
d_outbuf[2] => data_bus~13.DATAIN
d_outbuf[3] => data_bus~12.DATAIN
d_outbuf[4] => data_bus~11.DATAIN
d_outbuf[5] => data_bus~10.DATAIN
d_outbuf[6] => data_bus~9.DATAIN
d_outbuf[7] => data_bus~8.DATAIN
d_inbuf[0] <= d_inbuf[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[1] <= d_inbuf[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[2] <= d_inbuf[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[3] <= d_inbuf[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[4] <= d_inbuf[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[5] <= d_inbuf[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[6] <= d_inbuf[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[7] <= d_inbuf[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_bus[0] <= data_bus~15
data_bus[1] <= data_bus~14
data_bus[2] <= data_bus~13
data_bus[3] <= data_bus~12
data_bus[4] <= data_bus~11
data_bus[5] <= data_bus~10
data_bus[6] <= data_bus~9
data_bus[7] <= data_bus~8


|top_8255|inter_bus:inter_bus1
bus_con[0] => a_link.IN1
bus_con[1] => b_link.IN1
bus_con[2] => c_link.IN1
bus_con[3] => d_link.IN1
d_inbuf[0] => d_inbuf[0]~7.IN1
d_inbuf[1] => d_inbuf[1]~6.IN1
d_inbuf[2] => d_inbuf[2]~5.IN1
d_inbuf[3] => d_inbuf[3]~4.IN1
d_inbuf[4] => d_inbuf[4]~3.IN1
d_inbuf[5] => d_inbuf[5]~2.IN1
d_inbuf[6] => d_inbuf[6]~1.IN1
d_inbuf[7] => d_inbuf[7]~0.IN1
d_outbuf[0] <= data_bus_buf:d_bus1.d_inbuf
d_outbuf[1] <= data_bus_buf:d_bus1.d_inbuf
d_outbuf[2] <= data_bus_buf:d_bus1.d_inbuf
d_outbuf[3] <= data_bus_buf:d_bus1.d_inbuf
d_outbuf[4] <= data_bus_buf:d_bus1.d_inbuf
d_outbuf[5] <= data_bus_buf:d_bus1.d_inbuf
d_outbuf[6] <= data_bus_buf:d_bus1.d_inbuf
d_outbuf[7] <= data_bus_buf:d_bus1.d_inbuf
a_outbuf[0] <= data_bus_buf:a_bus1.d_inbuf
a_outbuf[1] <= data_bus_buf:a_bus1.d_inbuf
a_outbuf[2] <= data_bus_buf:a_bus1.d_inbuf
a_outbuf[3] <= data_bus_buf:a_bus1.d_inbuf
a_outbuf[4] <= data_bus_buf:a_bus1.d_inbuf
a_outbuf[5] <= data_bus_buf:a_bus1.d_inbuf
a_outbuf[6] <= data_bus_buf:a_bus1.d_inbuf
a_outbuf[7] <= data_bus_buf:a_bus1.d_inbuf
a_inbuf[0] => a_inbuf[0]~7.IN1
a_inbuf[1] => a_inbuf[1]~6.IN1
a_inbuf[2] => a_inbuf[2]~5.IN1
a_inbuf[3] => a_inbuf[3]~4.IN1
a_inbuf[4] => a_inbuf[4]~3.IN1
a_inbuf[5] => a_inbuf[5]~2.IN1
a_inbuf[6] => a_inbuf[6]~1.IN1
a_inbuf[7] => a_inbuf[7]~0.IN1
b_outbuf[0] <= data_bus_buf:b_bus1.d_inbuf
b_outbuf[1] <= data_bus_buf:b_bus1.d_inbuf
b_outbuf[2] <= data_bus_buf:b_bus1.d_inbuf
b_outbuf[3] <= data_bus_buf:b_bus1.d_inbuf
b_outbuf[4] <= data_bus_buf:b_bus1.d_inbuf
b_outbuf[5] <= data_bus_buf:b_bus1.d_inbuf
b_outbuf[6] <= data_bus_buf:b_bus1.d_inbuf
b_outbuf[7] <= data_bus_buf:b_bus1.d_inbuf
b_inbuf[0] => b_inbuf[0]~7.IN1
b_inbuf[1] => b_inbuf[1]~6.IN1
b_inbuf[2] => b_inbuf[2]~5.IN1
b_inbuf[3] => b_inbuf[3]~4.IN1
b_inbuf[4] => b_inbuf[4]~3.IN1
b_inbuf[5] => b_inbuf[5]~2.IN1
b_inbuf[6] => b_inbuf[6]~1.IN1
b_inbuf[7] => b_inbuf[7]~0.IN1
c_outbuf[0] <= data_bus_buf:c_bus1.d_inbuf
c_outbuf[1] <= data_bus_buf:c_bus1.d_inbuf
c_outbuf[2] <= data_bus_buf:c_bus1.d_inbuf
c_outbuf[3] <= data_bus_buf:c_bus1.d_inbuf
c_outbuf[4] <= data_bus_buf:c_bus1.d_inbuf
c_outbuf[5] <= data_bus_buf:c_bus1.d_inbuf
c_outbuf[6] <= data_bus_buf:c_bus1.d_inbuf
c_outbuf[7] <= data_bus_buf:c_bus1.d_inbuf
c_inbuf[0] => c_inbuf[0]~7.IN1
c_inbuf[1] => c_inbuf[1]~6.IN1
c_inbuf[2] => c_inbuf[2]~5.IN1
c_inbuf[3] => c_inbuf[3]~4.IN1
c_inbuf[4] => c_inbuf[4]~3.IN1
c_inbuf[5] => c_inbuf[5]~2.IN1
c_inbuf[6] => c_inbuf[6]~1.IN1
c_inbuf[7] => c_inbuf[7]~0.IN1


|top_8255|inter_bus:inter_bus1|data_bus_buf:d_bus1
lk_bus => data_bus~8.OE
lk_bus => data_bus~9.OE
lk_bus => data_bus~10.OE
lk_bus => data_bus~11.OE
lk_bus => data_bus~12.OE
lk_bus => data_bus~13.OE
lk_bus => data_bus~14.OE
lk_bus => data_bus~15.OE
lk_bus => d_inbuf[6]$latch.LATCH_ENABLE
lk_bus => d_inbuf[5]$latch.LATCH_ENABLE
lk_bus => d_inbuf[4]$latch.LATCH_ENABLE
lk_bus => d_inbuf[3]$latch.LATCH_ENABLE
lk_bus => d_inbuf[2]$latch.LATCH_ENABLE
lk_bus => d_inbuf[1]$latch.LATCH_ENABLE
lk_bus => d_inbuf[0]$latch.LATCH_ENABLE
lk_bus => d_inbuf[7]$latch.LATCH_ENABLE
d_outbuf[0] => data_bus~15.DATAIN
d_outbuf[1] => data_bus~14.DATAIN
d_outbuf[2] => data_bus~13.DATAIN
d_outbuf[3] => data_bus~12.DATAIN
d_outbuf[4] => data_bus~11.DATAIN
d_outbuf[5] => data_bus~10.DATAIN
d_outbuf[6] => data_bus~9.DATAIN
d_outbuf[7] => data_bus~8.DATAIN
d_inbuf[0] <= d_inbuf[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[1] <= d_inbuf[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[2] <= d_inbuf[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[3] <= d_inbuf[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[4] <= d_inbuf[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[5] <= d_inbuf[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[6] <= d_inbuf[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[7] <= d_inbuf[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_bus[0] <= data_bus~15
data_bus[1] <= data_bus~14
data_bus[2] <= data_bus~13
data_bus[3] <= data_bus~12
data_bus[4] <= data_bus~11
data_bus[5] <= data_bus~10
data_bus[6] <= data_bus~9
data_bus[7] <= data_bus~8


|top_8255|inter_bus:inter_bus1|data_bus_buf:a_bus1
lk_bus => data_bus~8.OE
lk_bus => data_bus~9.OE
lk_bus => data_bus~10.OE
lk_bus => data_bus~11.OE
lk_bus => data_bus~12.OE
lk_bus => data_bus~13.OE
lk_bus => data_bus~14.OE
lk_bus => data_bus~15.OE
lk_bus => d_inbuf[6]$latch.LATCH_ENABLE
lk_bus => d_inbuf[5]$latch.LATCH_ENABLE
lk_bus => d_inbuf[4]$latch.LATCH_ENABLE
lk_bus => d_inbuf[3]$latch.LATCH_ENABLE
lk_bus => d_inbuf[2]$latch.LATCH_ENABLE
lk_bus => d_inbuf[1]$latch.LATCH_ENABLE
lk_bus => d_inbuf[0]$latch.LATCH_ENABLE
lk_bus => d_inbuf[7]$latch.LATCH_ENABLE
d_outbuf[0] => data_bus~15.DATAIN
d_outbuf[1] => data_bus~14.DATAIN
d_outbuf[2] => data_bus~13.DATAIN
d_outbuf[3] => data_bus~12.DATAIN
d_outbuf[4] => data_bus~11.DATAIN
d_outbuf[5] => data_bus~10.DATAIN
d_outbuf[6] => data_bus~9.DATAIN
d_outbuf[7] => data_bus~8.DATAIN
d_inbuf[0] <= d_inbuf[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[1] <= d_inbuf[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[2] <= d_inbuf[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[3] <= d_inbuf[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[4] <= d_inbuf[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[5] <= d_inbuf[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[6] <= d_inbuf[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[7] <= d_inbuf[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_bus[0] <= data_bus~15
data_bus[1] <= data_bus~14
data_bus[2] <= data_bus~13
data_bus[3] <= data_bus~12
data_bus[4] <= data_bus~11
data_bus[5] <= data_bus~10
data_bus[6] <= data_bus~9
data_bus[7] <= data_bus~8


|top_8255|inter_bus:inter_bus1|data_bus_buf:b_bus1
lk_bus => data_bus~8.OE
lk_bus => data_bus~9.OE
lk_bus => data_bus~10.OE
lk_bus => data_bus~11.OE
lk_bus => data_bus~12.OE
lk_bus => data_bus~13.OE
lk_bus => data_bus~14.OE
lk_bus => data_bus~15.OE
lk_bus => d_inbuf[6]$latch.LATCH_ENABLE
lk_bus => d_inbuf[5]$latch.LATCH_ENABLE
lk_bus => d_inbuf[4]$latch.LATCH_ENABLE
lk_bus => d_inbuf[3]$latch.LATCH_ENABLE
lk_bus => d_inbuf[2]$latch.LATCH_ENABLE
lk_bus => d_inbuf[1]$latch.LATCH_ENABLE
lk_bus => d_inbuf[0]$latch.LATCH_ENABLE
lk_bus => d_inbuf[7]$latch.LATCH_ENABLE
d_outbuf[0] => data_bus~15.DATAIN
d_outbuf[1] => data_bus~14.DATAIN
d_outbuf[2] => data_bus~13.DATAIN
d_outbuf[3] => data_bus~12.DATAIN
d_outbuf[4] => data_bus~11.DATAIN
d_outbuf[5] => data_bus~10.DATAIN
d_outbuf[6] => data_bus~9.DATAIN
d_outbuf[7] => data_bus~8.DATAIN
d_inbuf[0] <= d_inbuf[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[1] <= d_inbuf[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[2] <= d_inbuf[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[3] <= d_inbuf[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[4] <= d_inbuf[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[5] <= d_inbuf[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[6] <= d_inbuf[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
d_inbuf[7] <= d_inbuf[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_bus[0] <= data_bus~15
data_bus[1] <= data_bus~14
data_bus[2] <= data_bus~13