top_8255.tan.qmsg

用Verilog实现8255芯片功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "a1 register bb_port:bb_port1\|b_inbuf\[6\] register inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\] 39.06 MHz 25.6 ns Internal " "Info: Clock \"a1\" has Internal fmax of 39.06 MHz between source register \"bb_port:bb_port1\|b_inbuf\[6\]\" and destination register \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\]\" (period= 25.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest register register " "Info: + Longest register to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bb_port:bb_port1\|b_inbuf\[6\] 1 REG LC7_C4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C4; Fanout = 2; REG Node = 'bb_port:bb_port1\|b_inbuf\[6\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { bb_port:bb_port1|b_inbuf[6] } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3255 2 COMB LC6_C4 2 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC6_C4; Fanout = 2; COMB Node = 'inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3255'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 4.100 ns inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3283 3 COMB LC1_C5 1 " "Info: 3: + IC(1.000 ns) + CELL(1.400 ns) = 4.100 ns; Loc. = LC1_C5; Fanout = 1; COMB Node = 'inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3283'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 6.500 ns inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\] 4 REG LC5_C6 1 " "Info: 4: + IC(1.000 ns) + CELL(1.400 ns) = 6.500 ns; Loc. = LC5_C6; Fanout = 1; REG Node = 'inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 64.62 % ) " "Info: Total cell delay = 4.200 ns ( 64.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 35.38 % ) " "Info: Total interconnect delay = 2.300 ns ( 35.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } { 0.000ns 0.300ns 1.000ns 1.000ns } { 0.000ns 1.400ns 1.400ns 1.400ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.800 ns - Smallest " "Info: - Smallest clock skew is -2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a1 destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"a1\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a1 1 CLK PIN_56 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 7; CLK Node = 'a1'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { a1 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 3.400 ns r_w_con:r_w_con1\|bus_con\[2\]~491 2 COMB LC3_B11 20 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 3.400 ns; Loc. = LC3_B11; Fanout = 20; COMB Node = 'r_w_con:r_w_con1\|bus_con\[2\]~491'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { a1 r_w_con:r_w_con1|bus_con[2]~491 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 271 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.400 ns) 6.800 ns r_w_con:r_w_con1\|bus_con\[2\]~493 3 COMB LC4_A4 24 " "Info: 3: + IC(2.000 ns) + CELL(1.400 ns) = 6.800 ns; Loc. = LC4_A4; Fanout = 24; COMB Node = 'r_w_con:r_w_con1\|bus_con\[2\]~493'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { r_w_con:r_w_con1|bus_con[2]~491 r_w_con:r_w_con1|bus_con[2]~493 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 271 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.600 ns) 10.000 ns inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\] 4 REG LC5_C6 1 " "Info: 4: + IC(1.600 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = LC5_C6; Fanout = 1; REG Node = 'inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { r_w_con:r_w_con1|bus_con[2]~493 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns ( 64.00 % ) " "Info: Total cell delay = 6.400 ns ( 64.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 36.00 % ) " "Info: Total interconnect delay = 3.600 ns ( 36.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { a1 r_w_con:r_w_con1|bus_con[2]~491 r_w_con:r_w_con1|bus_con[2]~493 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { a1 a1~out r_w_con:r_w_con1|bus_con[2]~491 r_w_con:r_w_con1|bus_con[2]~493 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } { 0.000ns 0.000ns 0.000ns 2.000ns 1.600ns } { 0.000ns 2.000ns 1.400ns 1.400ns 1.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a1 source 12.800 ns - Longest register " "Info: - Longest clock path from clock \"a1\" to source register is 12.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a1 1 CLK PIN_56 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 7; CLK Node = 'a1'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { a1 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 3.400 ns r_w_con:r_w_con1\|con~9 2 COMB LC5_B11 6 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 3.400 ns; Loc. = LC5_B11; Fanout = 6; COMB Node = 'r_w_con:r_w_con1\|con~9'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { a1 r_w_con:r_w_con1|con~9 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 290 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.600 ns) 6.400 ns r_w_con:r_w_con1\|con_word\[7\] 3 REG LC7_B3 5 " "Info: 3: + IC(1.400 ns) + CELL(1.600 ns) = 6.400 ns; Loc. = LC7_B3; Fanout = 5; REG Node = 'r_w_con:r_w_con1\|con_word\[7\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { r_w_con:r_w_con1|con~9 r_w_con:r_w_con1|con_word[7] } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 9.200 ns r_w_con:r_w_con1\|b_mode_io 4 REG LC1_B11 17 " "Info: 4: + IC(1.200 ns) + CELL(1.600 ns) = 9.200 ns; Loc. = LC1_B11; Fanout = 17; REG Node = 'r_w_con:r_w_con1\|b_mode_io'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { r_w_con:r_w_con1|con_word[7] r_w_con:r_w_con1|b_mode_io } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 279 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.600 ns) 12.800 ns bb_port:bb_port1\|b_inbuf\[6\] 5 REG LC7_C4 2 " "Info: 5: + IC(2.000 ns) + CELL(1.600 ns) = 12.800 ns; Loc. = LC7_C4; Fanout = 2; REG Node = 'bb_port:bb_port1\|b_inbuf\[6\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { r_w_con:r_w_con1|b_mode_io bb_port:bb_port1|b_inbuf[6] } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.200 ns ( 64.06 % ) " "Info: Total cell delay = 8.200 ns ( 64.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 35.94 % ) " "Info: Total interconnect delay = 4.600 ns ( 35.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "12.800 ns" { a1 r_w_con:r_w_con1|con~9 r_w_con:r_w_con1|con_word[7] r_w_con:r_w_con1|b_mode_io bb_port:bb_port1|b_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "12.800 ns" { a1 a1~out r_w_con:r_w_con1|con~9 r_w_con:r_w_con1|con_word[7] r_w_con:r_w_con1|b_mode_io bb_port:bb_port1|b_inbuf[6] } { 0.000ns 0.000ns 0.000ns 1.400ns 1.200ns 2.000ns } { 0.000ns 2.000ns 1.400ns 1.600ns 1.600ns 1.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { a1 r_w_con:r_w_con1|bus_con[2]~491 r_w_con:r_w_con1|bus_con[2]~493 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { a1 a1~out r_w_con:r_w_con1|bus_con[2]~491 r_w_con:r_w_con1|bus_con[2]~493 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } { 0.000ns 0.000ns 0.000ns 2.000ns 1.600ns } { 0.000ns 2.000ns 1.400ns 1.400ns 1.600ns } } } { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "12.800 ns" { a1 r_w_con:r_w_con1|con~9 r_w_con:r_w_con1|con_word[7] r_w_con:r_w_con1|b_mode_io bb_port:bb_port1|b_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "12.800 ns" { a1 a1~out r_w_con:r_w_con1|con~9 r_w_con:r_w_con1|con_word[7] r_w_con:r_w_con1|b_mode_io bb_port:bb_port1|b_inbuf[6] } { 0.000ns 0.000ns 0.000ns 1.400ns 1.200ns 2.000ns } { 0.000ns 2.000ns 1.400ns 1.600ns 1.600ns 1.600ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.500 ns + " "Info: + Micro setup delay of destination is 3.500 ns" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 -1 0 } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } { 0.000ns 0.300ns 1.000ns 1.000ns } { 0.000ns 1.400ns 1.400ns 1.400ns } } } { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { a1 r_w_con:r_w_con1|bus_con[2]~491 r_w_con:r_w_con1|bus_con[2]~493 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { a1 a1~out r_w_con:r_w_con1|bus_con[2]~491 r_w_con:r_w_con1|bus_con[2]~493 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } { 0.000ns 0.000ns 0.000ns 2.000ns 1.600ns } { 0.000ns 2.000ns 1.400ns 1.400ns 1.600ns } } } { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "12.800 ns" { a1 r_w_con:r_w_con1|con~9 r_w_con:r_w_con1|con_word[7] r_w_con:r_w_con1|b_mode_io bb_port:bb_port1|b_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "12.800 ns" { a1 a1~out r_w_con:r_w_con1|con~9 r_w_con:r_w_con1|con_word[7] r_w_con:r_w_con1|b_mode_io bb_port:bb_port1|b_inbuf[6] } { 0.000ns 0.000ns 0.000ns 1.400ns 1.200ns 2.000ns } { 0.000ns 2.000ns 1.400ns 1.600ns 1.600ns 1.600ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "a0 register bb_port:bb_port1\|b_inbuf\[6\] register inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\] 39.06 MHz 25.6 ns Internal " "Info: Clock \"a0\" has Internal fmax of 39.06 MHz between source register \"bb_port:bb_port1\|b_inbuf\[6\]\" and destination register \"inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\]\" (period= 25.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest register register " "Info: + Longest register to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bb_port:bb_port1\|b_inbuf\[6\] 1 REG LC7_C4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C4; Fanout = 2; REG Node = 'bb_port:bb_port1\|b_inbuf\[6\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { bb_port:bb_port1|b_inbuf[6] } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 465 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3255 2 COMB LC6_C4 2 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC6_C4; Fanout = 2; COMB Node = 'inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3255'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 4.100 ns inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3283 3 COMB LC1_C5 1 " "Info: 3: + IC(1.000 ns) + CELL(1.400 ns) = 4.100 ns; Loc. = LC1_C5; Fanout = 1; COMB Node = 'inter_bus:inter_bus1\|data_bus_buf:c_bus1\|data_bus~3283'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 6.500 ns inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\] 4 REG LC5_C6 1 " "Info: 4: + IC(1.000 ns) + CELL(1.400 ns) = 6.500 ns; Loc. = LC5_C6; Fanout = 1; REG Node = 'inter_bus:inter_bus1\|data_bus_buf:c_bus1\|d_inbuf\[6\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 221 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 64.62 % ) " "Info: Total cell delay = 4.200 ns ( 64.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 35.38 % ) " "Info: Total interconnect delay = 2.300 ns ( 35.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { bb_port:bb_port1|b_inbuf[6] inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3255 inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~3283 inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] } { 0.000ns 0.300ns 1.000ns 1.000ns } { 0.000ns 1.400ns 1.400ns 1.400ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.800 ns - Smallest " "Info: - Smallest clock skew is -2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a0 destination 10.200 ns + Shortest register " "Info: + Shortest clock path from clock \"a0\" to destination register is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a0 1 CLK PIN_55 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 7; CLK Node = 'a0'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { a0 } "NODE_NAME" } } { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 3.600 ns r_w_con:r_w_con1\|bus_con\[2\]~491 2 COMB LC3_B11 20 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 3.600 ns; Loc. = LC3_B11; Fanout = 20; COMB Node = 'r_w_con:r_w_con1\|bus_con\[2\]~491'" {  } { { "d:/eda/q