top_8255.tan.qmsg

用Verilog实现8255芯片功能

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "a1 " "Info: Assuming node \"a1\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "a0 " "Info: Assuming node \"a0\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "cs_n " "Info: Assuming node \"cs_n\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "wr_n " "Info: Assuming node \"wr_n\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "rd_n " "Info: Assuming node \"rd_n\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "33 " "Warning: Found 33 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|c_upper_io " "Info: Detected ripple clock \"r_w_con:r_w_con1\|c_upper_io\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 283 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|c_upper_io" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|c_lower_io " "Info: Detected ripple clock \"r_w_con:r_w_con1\|c_lower_io\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 283 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|c_lower_io" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|con_word\[1\] " "Info: Detected ripple clock \"r_w_con:r_w_con1\|con_word\[1\]\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|con_word\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|con_word\[3\] " "Info: Detected ripple clock \"r_w_con:r_w_con1\|con_word\[3\]\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|con_word\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|con_word\[2\] " "Info: Detected ripple clock \"r_w_con:r_w_con1\|con_word\[2\]\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|con_word\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|con_word\[7\] " "Info: Detected ripple clock \"r_w_con:r_w_con1\|con_word\[7\]\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 291 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|con_word\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|b_mode_io " "Info: Detected ripple clock \"r_w_con:r_w_con1\|b_mode_io\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 279 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|b_mode_io" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "r_w_con:r_w_con1\|a_mode_io " "Info: Detected ripple clock \"r_w_con:r_w_con1\|a_mode_io\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 275 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|a_mode_io" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|bus_con\[0\]~494 " "Info: Detected gated clock \"r_w_con:r_w_con1\|bus_con\[0\]~494\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 271 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|bus_con\[0\]~494" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|bus_con\[2\]~493 " "Info: Detected gated clock \"r_w_con:r_w_con1\|bus_con\[2\]~493\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 271 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|bus_con\[2\]~493" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|bus_con\[1\]~492 " "Info: Detected gated clock \"r_w_con:r_w_con1\|bus_con\[1\]~492\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 271 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|bus_con\[1\]~492" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~748 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~748\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~748" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~746 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~746\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~746" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~744 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~744\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~744" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~743 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~743\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~743" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~741 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~741\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~741" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~740 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~740\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~740" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~738 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~738\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~738" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~737 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~737\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~737" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~735 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~735\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~735" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~734 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~734\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~734" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~732 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~732\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~732" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~731 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~731\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~731" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|con~9 " "Info: Detected gated clock \"r_w_con:r_w_con1\|con~9\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 290 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|con~9" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~729 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~729\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~729" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "cc_port:cc_port1\|always2~728 " "Info: Detected gated clock \"cc_port:cc_port1\|always2~728\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "cc_port:cc_port1\|always2~728" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|c_set_rst\[4\] " "Info: Detected gated clock \"r_w_con:r_w_con1\|c_set_rst\[4\]\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 284 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|c_set_rst\[4\]" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "bb_port:bb_port1\|always0~12 " "Info: Detected gated clock \"bb_port:bb_port1\|always0~12\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "bb_port:bb_port1\|always0~12" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "aa_port:aa_port1\|always0~0 " "Info: Detected gated clock \"aa_port:aa_port1\|always0~0\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "aa_port:aa_port1\|always0~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "bb_port:bb_port1\|always0~11 " "Info: Detected gated clock \"bb_port:bb_port1\|always0~11\" as buffer" {  } { { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "bb_port:bb_port1\|always0~11" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|bus_con\[2\]~491 " "Info: Detected gated clock \"r_w_con:r_w_con1\|bus_con\[2\]~491\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 271 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|bus_con\[2\]~491" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|bus_con\[0\]~490 " "Info: Detected gated clock \"r_w_con:r_w_con1\|bus_con\[0\]~490\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 271 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|bus_con\[0\]~490" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "r_w_con:r_w_con1\|lk_bus " "Info: Detected gated clock \"r_w_con:r_w_con1\|lk_bus\" as buffer" {  } { { "top_8255.v" "" { Text "F:/cfm/8255-quantus/top.v/top_8255.v" 267 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "r_w_con:r_w_con1\|lk_bus" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}