top_8255.map.rpt

用Verilog实现8255芯片功能

Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[0]"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(364): inferring latch(es) for variable "a_mode_io", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(275): inferred latch for "a_mode_io"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(371): inferring latch(es) for variable "b_mode_io", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(279): inferred latch for "b_mode_io"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(387): inferring latch(es) for variable "c_upper_io", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(283): inferred latch for "c_upper_io"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(387): inferring latch(es) for variable "c_lower_io", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(283): inferred latch for "c_lower_io"
Info: Elaborating entity "aa_port" for hierarchy "aa_port:aa_port1"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(441): inferring latch(es) for variable "a_inbuf", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[4]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(421): inferred latch for "a_inbuf[0]"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(441): inferring latch(es) for variable "a_out", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[4]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(435): inferred latch for "a_out[0]"
Info: Elaborating entity "bb_port" for hierarchy "bb_port:bb_port1"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(484): inferring latch(es) for variable "b_inbuf", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[4]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(465): inferred latch for "b_inbuf[0]"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(484): inferring latch(es) for variable "b_out", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[4]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(478): inferred latch for "b_out[0]"
Info: Elaborating entity "cc_port" for hierarchy "cc_port:cc_port1"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(521): inferring latch(es) for variable "c_inbuf", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[0]"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(531): inferring latch(es) for variable "c_inbuf", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(511): inferred latch for "c_inbuf[4]"
Warning (10235): Verilog HDL Always Construct warning at top_8255.v(549): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at top_8255.v(551): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(540): inferring latch(es) for variable "c_out", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[4]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(546): inferred latch for "c_out[0]"
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~24" that feeds logic to an OR gate
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~28" that feeds logic to an OR gate
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~32" that feeds logic to an OR gate
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~36" that feeds logic to an OR gate
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~40" that feeds logic to an OR gate
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~44" that feeds logic to an OR gate
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~48" that feeds logic to an OR gate
Warning: Converting TRI node "inter_bus:inter_bus1|data_bus_buf:c_bus1|data_bus~52" that feeds logic to an OR gate
Warning: Latch cc_port:cc_port1|c_out[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch cc_port:cc_port1|c_out[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch cc_port:cc_port1|c_out[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch cc_port:cc_port1|c_out[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch cc_port:cc_port1|c_out[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch cc_port:cc_port1|c_out[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch cc_port:cc_port1|c_out[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch cc_port:cc_port1|c_out[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|c_set_rst[4]
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Warning: Latch inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal r_w_con:r_w_con1|lk_bus
Info: Implemented 229 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 0 output pins
    Info: Implemented 32 bidirectional pins
    Info: Implemented 191 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 87 warnings
    Info: Processing ended: Thu Nov 09 19:18:51 2006
    Info: Elapsed time: 00:00:02