📄 top_8255.map.rpt
字号:
+-----------------------------------------------------+------------------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+------------------------------+------------------------+
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[0] ; r_w_con:r_w_con1|lk_bus ; yes ;
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[1] ; r_w_con:r_w_con1|lk_bus ; yes ;
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[2] ; r_w_con:r_w_con1|lk_bus ; yes ;
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[3] ; r_w_con:r_w_con1|lk_bus ; yes ;
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[4] ; r_w_con:r_w_con1|lk_bus ; yes ;
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[5] ; r_w_con:r_w_con1|lk_bus ; yes ;
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[6] ; r_w_con:r_w_con1|lk_bus ; yes ;
; inter_bus:inter_bus1|data_bus_buf:d_bus1|d_inbuf[7] ; r_w_con:r_w_con1|lk_bus ; yes ;
; aa_port:aa_port1|a_out[0] ; aa_port:aa_port1|always0~0 ; yes ;
; r_w_con:r_w_con1|a_mode_io ; r_w_con:r_w_con1|con_word[7] ; yes ;
; aa_port:aa_port1|a_out[1] ; aa_port:aa_port1|always0~0 ; yes ;
; aa_port:aa_port1|a_out[2] ; aa_port:aa_port1|always0~0 ; yes ;
; aa_port:aa_port1|a_out[3] ; aa_port:aa_port1|always0~0 ; yes ;
; aa_port:aa_port1|a_out[4] ; aa_port:aa_port1|always0~0 ; yes ;
; aa_port:aa_port1|a_out[5] ; aa_port:aa_port1|always0~0 ; yes ;
; aa_port:aa_port1|a_out[6] ; aa_port:aa_port1|always0~0 ; yes ;
; aa_port:aa_port1|a_out[7] ; aa_port:aa_port1|always0~0 ; yes ;
; bb_port:bb_port1|b_out[0] ; bb_port:bb_port1|always0~0 ; yes ;
; r_w_con:r_w_con1|b_mode_io ; r_w_con:r_w_con1|con_word[7] ; yes ;
; bb_port:bb_port1|b_out[1] ; bb_port:bb_port1|always0~0 ; yes ;
; bb_port:bb_port1|b_out[2] ; bb_port:bb_port1|always0~0 ; yes ;
; bb_port:bb_port1|b_out[3] ; bb_port:bb_port1|always0~0 ; yes ;
; bb_port:bb_port1|b_out[4] ; bb_port:bb_port1|always0~0 ; yes ;
; bb_port:bb_port1|b_out[5] ; bb_port:bb_port1|always0~0 ; yes ;
; bb_port:bb_port1|b_out[6] ; bb_port:bb_port1|always0~0 ; yes ;
; bb_port:bb_port1|b_out[7] ; bb_port:bb_port1|always0~0 ; yes ;
; cc_port:cc_port1|c_out[0] ; cc_port:cc_port1|always2~16 ; yes ;
; r_w_con:r_w_con1|c_lower_io ; r_w_con:r_w_con1|con_word[7] ; yes ;
; cc_port:cc_port1|c_out[1] ; cc_port:cc_port1|always2~14 ; yes ;
; cc_port:cc_port1|c_out[2] ; cc_port:cc_port1|always2~12 ; yes ;
; cc_port:cc_port1|c_out[3] ; cc_port:cc_port1|always2~10 ; yes ;
; cc_port:cc_port1|c_out[4] ; cc_port:cc_port1|always2~8 ; yes ;
; r_w_con:r_w_con1|c_upper_io ; r_w_con:r_w_con1|con_word[7] ; yes ;
; cc_port:cc_port1|c_out[5] ; cc_port:cc_port1|always2~6 ; yes ;
; cc_port:cc_port1|c_out[6] ; cc_port:cc_port1|always2~4 ; yes ;
; cc_port:cc_port1|c_out[7] ; cc_port:cc_port1|always2~2 ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[0] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; r_w_con:r_w_con1|con_word[4] ; r_w_con:r_w_con1|con ; yes ;
; r_w_con:r_w_con1|con_word[7] ; r_w_con:r_w_con1|con ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[1] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[2] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[3] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[4] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[5] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[6] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[7] ; r_w_con:r_w_con1|bus_con[0] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[0] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; r_w_con:r_w_con1|con_word[1] ; r_w_con:r_w_con1|con ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[1] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[2] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[3] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[4] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[5] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[6] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[7] ; r_w_con:r_w_con1|bus_con[1] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[0] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; r_w_con:r_w_con1|con_word[0] ; r_w_con:r_w_con1|con ; yes ;
; r_w_con:r_w_con1|con_word[3] ; r_w_con:r_w_con1|con ; yes ;
; r_w_con:r_w_con1|con_word[2] ; r_w_con:r_w_con1|con ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[1] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[2] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[3] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[4] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[5] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[7] ; r_w_con:r_w_con1|bus_con[2] ; yes ;
; data_bus_buf:data_buf1|d_inbuf[4] ; r_w_con:r_w_con1|lk_bus ; yes ;
; data_bus_buf:data_buf1|d_inbuf[7] ; r_w_con:r_w_con1|lk_bus ; yes ;
; data_bus_buf:data_buf1|d_inbuf[1] ; r_w_con:r_w_con1|lk_bus ; yes ;
; data_bus_buf:data_buf1|d_inbuf[0] ; r_w_con:r_w_con1|lk_bus ; yes ;
; data_bus_buf:data_buf1|d_inbuf[3] ; r_w_con:r_w_con1|lk_bus ; yes ;
; data_bus_buf:data_buf1|d_inbuf[2] ; r_w_con:r_w_con1|lk_bus ; yes ;
; cc_port:cc_port1|c_inbuf[0] ; r_w_con:r_w_con1|c_lower_io ; yes ;
; bb_port:bb_port1|b_inbuf[0] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[0] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; cc_port:cc_port1|c_inbuf[1] ; r_w_con:r_w_con1|c_lower_io ; yes ;
; bb_port:bb_port1|b_inbuf[1] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[1] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; cc_port:cc_port1|c_inbuf[2] ; r_w_con:r_w_con1|c_lower_io ; yes ;
; bb_port:bb_port1|b_inbuf[2] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[2] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; cc_port:cc_port1|c_inbuf[3] ; r_w_con:r_w_con1|c_lower_io ; yes ;
; bb_port:bb_port1|b_inbuf[3] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[3] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; cc_port:cc_port1|c_inbuf[4] ; r_w_con:r_w_con1|c_upper_io ; yes ;
; bb_port:bb_port1|b_inbuf[4] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[4] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; cc_port:cc_port1|c_inbuf[5] ; r_w_con:r_w_con1|c_upper_io ; yes ;
; bb_port:bb_port1|b_inbuf[5] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[5] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; data_bus_buf:data_buf1|d_inbuf[5] ; r_w_con:r_w_con1|lk_bus ; yes ;
; cc_port:cc_port1|c_inbuf[6] ; r_w_con:r_w_con1|c_upper_io ; yes ;
; bb_port:bb_port1|b_inbuf[6] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[6] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; data_bus_buf:data_buf1|d_inbuf[6] ; r_w_con:r_w_con1|lk_bus ; yes ;
; cc_port:cc_port1|c_inbuf[7] ; r_w_con:r_w_con1|c_upper_io ; yes ;
; bb_port:bb_port1|b_inbuf[7] ; r_w_con:r_w_con1|b_mode_io ; yes ;
; aa_port:aa_port1|a_inbuf[7] ; r_w_con:r_w_con1|a_mode_io ; yes ;
; Number of user-specified and inferred latches = 98 ; ; ;
+-----------------------------------------------------+------------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Nov 09 19:18:49 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top_8255 -c top_8255
Info: Found 7 design units, including 7 entities, in source file top_8255.v
Info: Found entity 1: top_8255
Info: Found entity 2: inter_bus
Info: Found entity 3: data_bus_buf
Info: Found entity 4: r_w_con
Info: Found entity 5: aa_port
Info: Found entity 6: bb_port
Info: Found entity 7: cc_port
Info: Elaborating entity "top_8255" for the top level hierarchy
Info: Elaborating entity "data_bus_buf" for hierarchy "data_bus_buf:data_buf1"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(222): inferring latch(es) for variable "d_inbuf", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[4]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[3]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[2]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[1]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(221): inferred latch for "d_inbuf[0]"
Info: Elaborating entity "inter_bus" for hierarchy "inter_bus:inter_bus1"
Info: Elaborating entity "r_w_con" for hierarchy "r_w_con:r_w_con1"
Warning (10240): Verilog HDL Always Construct warning at top_8255.v(357): inferring latch(es) for variable "con_word", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[7]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[6]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[5]"
Info (10041): Verilog HDL or VHDL info at top_8255.v(291): inferred latch for "con_word[4]"
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -