transcript

用Verilog实现8255芯片功能

# Compile of top_8255.v was successful.
# Compile of tb_top_8255.v failed with 1 errors.
# 2 compiles, 1 failed with 1 error. 
# Compile of tb_top_8255.v failed with 1 errors.
# Compile of tb_top_8255.v was successful.
view -new wave
# .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs
vsim work.tb_top_8255
# vsim work.tb_top_8255 
# Loading work.tb_top_8255
# Loading work.top_8255
# ** Warning: (vsim-3009) [TSCALE] - Module 'top_8255' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_top_8255/abcd
# Loading work.data_bus_buf
# ** Warning: (vsim-3009) [TSCALE] - Module 'data_bus_buf' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_top_8255/abcd/data_buf1
# Loading work.inter_bus
# ** Warning: (vsim-3009) [TSCALE] - Module 'inter_bus' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_top_8255/abcd/inter_bus1
# Loading work.r_w_con
# ** Warning: (vsim-3009) [TSCALE] - Module 'r_w_con' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_top_8255/abcd/r_w_con1
# Loading work.aa_port
# ** Warning: (vsim-3009) [TSCALE] - Module 'aa_port' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_top_8255/abcd/aa_port1
# Loading work.bb_port
# ** Warning: (vsim-3009) [TSCALE] - Module 'bb_port' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_top_8255/abcd/bb_port1
# Loading work.cc_port
# ** Warning: (vsim-3009) [TSCALE] - Module 'cc_port' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_top_8255/abcd/cc_port1
add wave sim:/tb_top_8255/rst_n
add wave sim:/tb_top_8255/cs_n
add wave sim:/tb_top_8255/a1
add wave sim:/tb_top_8255/a0
add wave sim:/tb_top_8255/wr_n
add wave sim:/tb_top_8255/rd_n
add wave sim:/tb_top_8255/link_bus_cpu
add wave sim:/tb_top_8255/cpu_data
add wave sim:/tb_top_8255/data_bus
add wave sim:/tb_top_8255/link_bus_a
add wave sim:/tb_top_8255/a_per_data
add wave sim:/tb_top_8255/a_bus
add wave sim:/tb_top_8255/link_bus_b
add wave sim:/tb_top_8255/b_per_data
add wave sim:/tb_top_8255/b_bus
add wave sim:/tb_top_8255/lk_bus_c_upper
add wave sim:/tb_top_8255/lk_bus_c_lower
add wave sim:/tb_top_8255/c_per_data
add wave sim:/tb_top_8255/c_bus
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs wave.do
run -all
# Compile of top_8255.v was successful.
# Compile of tb_top_8255.v was successful.
# 2 compiles, 0 failed with no errors. 
# Break key hit 
# Break at F:/cfm/top.v/top_8255.v line 221
run -continue
# Break key hit 
# Break at F:/cfm/top.v/top_8255.v line 221
run -all
# Break key hit 
# Break at F:/cfm/top.v/top_8255.v line 221
# Compile of top_8255.v was successful.
# Compile of tb_top_8255.v was successful.
# 2 compiles, 0 failed with no errors. 
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_2.wf.clip.cs wave.do
run -all
# Break key hit 
# Break at F:/cfm/top.v/top_8255.v line 221
run -continue
# Break key hit 
# Break at F:/cfm/top.v/top_8255.v line 221