top_8255.tan.summary

来自「用Verilog实现8255芯片功能」· SUMMARY 代码 · 共 157 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.800 ns
From           : a1
To             : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6]
From Clock     : --
To Clock       : rd_n
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 25.600 ns
From           : cc_port:cc_port1|c_out[7]
To             : c_bus[7]
From Clock     : cs_n
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.100 ns
From           : rd_n
To             : data_bus[0]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 9.300 ns
From           : a1
To             : cc_port:cc_port1|c_out[2]
From Clock     : --
To Clock       : cs_n
Failed Paths   : 0

Type           : Clock Setup: 'cs_n'
Slack          : N/A
Required Time  : None
Actual Time    : 39.06 MHz ( period = 25.600 ns )
From           : bb_port:bb_port1|b_inbuf[6]
To             : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6]
From Clock     : cs_n
To Clock       : cs_n
Failed Paths   : 0

Type           : Clock Setup: 'a0'
Slack          : N/A
Required Time  : None
Actual Time    : 39.06 MHz ( period = 25.600 ns )
From           : bb_port:bb_port1|b_inbuf[6]
To             : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6]
From Clock     : a0
To Clock       : a0
Failed Paths   : 0

Type           : Clock Setup: 'a1'
Slack          : N/A
Required Time  : None
Actual Time    : 39.06 MHz ( period = 25.600 ns )
From           : bb_port:bb_port1|b_inbuf[6]
To             : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6]
From Clock     : a1
To Clock       : a1
Failed Paths   : 0

Type           : Clock Setup: 'rd_n'
Slack          : N/A
Required Time  : None
Actual Time    : 62.50 MHz ( period = 16.000 ns )
From           : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[1]
To             : cc_port:cc_port1|c_out[1]
From Clock     : rd_n
To Clock       : rd_n
Failed Paths   : 0

Type           : Clock Setup: 'wr_n'
Slack          : N/A
Required Time  : None
Actual Time    : 63.29 MHz ( period = 15.800 ns )
From           : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[1]
To             : cc_port:cc_port1|c_out[1]
From Clock     : wr_n
To Clock       : wr_n
Failed Paths   : 0

Type           : Clock Hold: 'a1'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : r_w_con:r_w_con1|con_word[0]
To             : cc_port:cc_port1|c_out[3]
From Clock     : a1
To Clock       : a1
Failed Paths   : 44

Type           : Clock Hold: 'a0'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : r_w_con:r_w_con1|con_word[0]
To             : cc_port:cc_port1|c_out[3]
From Clock     : a0
To Clock       : a0
Failed Paths   : 44

Type           : Clock Hold: 'cs_n'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : r_w_con:r_w_con1|con_word[0]
To             : cc_port:cc_port1|c_out[3]
From Clock     : cs_n
To Clock       : cs_n
Failed Paths   : 44

Type           : Clock Hold: 'rd_n'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[4]
To             : cc_port:cc_port1|c_out[4]
From Clock     : rd_n
To Clock       : rd_n
Failed Paths   : 1

Type           : Clock Hold: 'wr_n'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[4]
To             : cc_port:cc_port1|c_out[4]
From Clock     : wr_n
To Clock       : wr_n
Failed Paths   : 1

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 134

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