top_8255.tan.rpt

用Verilog实现8255芯片功能

; Clock Hold: 'a0'             ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; r_w_con:r_w_con1|con_word[0]                        ; cc_port:cc_port1|c_out[3]                           ; a0         ; a0       ; 44           ;
; Clock Hold: 'cs_n'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; r_w_con:r_w_con1|con_word[0]                        ; cc_port:cc_port1|c_out[3]                           ; cs_n       ; cs_n     ; 44           ;
; Clock Hold: 'rd_n'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[4] ; cc_port:cc_port1|c_out[4]                           ; rd_n       ; rd_n     ; 1            ;
; Clock Hold: 'wr_n'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[4] ; cc_port:cc_port1|c_out[4]                           ; wr_n       ; wr_n     ; 1            ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                     ;                                                     ;            ;          ; 134          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------+-----------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K10TC144-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; a1              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; a0              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; cs_n            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; wr_n            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; rd_n            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'a1'                                                                                                                                                                                                                                                ;
+-------+----------------------------------+-----------------------------------------------------+-----------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                                                ; To                                                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+-----------------------------------------------------+-----------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 39.06 MHz ( period = 25.600 ns ) ; bb_port:bb_port1|b_inbuf[6]                         ; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[6] ; a1         ; a1       ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 39.37 MHz ( period = 25.400 ns ) ; bb_port:bb_port1|b_inbuf[5]                         ; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[5] ; a1         ; a1       ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 39.37 MHz ( period = 25.400 ns ) ; bb_port:bb_port1|b_inbuf[7]                         ; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[7] ; a1         ; a1       ; None                        ; None                      ; 6.400 ns                ;
; N/A   ; 40.00 MHz ( period = 25.000 ns ) ; bb_port:bb_port1|b_inbuf[7]                         ; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[7] ; a1         ; a1       ; None                        ; None                      ; 6.500 ns                ;
; N/A   ; 40.65 MHz ( period = 24.600 ns ) ; bb_port:bb_port1|b_inbuf[4]                         ; inter_bus:inter_bus1|data_bus_buf:c_bus1|d_inbuf[4] ; a1         ; a1       ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 40.65 MHz ( period = 24.600 ns ) ; bb_port:bb_port1|b_inbuf[4]                         ; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[4] ; a1         ; a1       ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 40.65 MHz ( period = 24.600 ns ) ; cc_port:cc_port1|c_inbuf[4]                         ; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[4] ; a1         ; a1       ; None                        ; None                      ; 5.100 ns                ;
; N/A   ; 40.98 MHz ( period = 24.400 ns ) ; cc_port:cc_port1|c_inbuf[6]                         ; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[6] ; a1         ; a1       ; None                        ; None                      ; 5.800 ns                ;
; N/A   ; 41.32 MHz ( period = 24.200 ns ) ; cc_port:cc_port1|c_inbuf[5]                         ; inter_bus:inter_bus1|data_bus_buf:b_bus1|d_inbuf[5] ; a1         ; a1       ; None                        ; None                      ; 5.800 ns                ;
; N/A   ; 42.02 MHz ( period = 23.800 ns ) ; bb_port:bb_port1|b_inbuf[6]                         ; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[6] ; a1         ; a1       ; None                        ; None                      ; 5.800 ns                ;
; N/A   ; 43.10 MHz ( period = 23.200 ns ) ; cc_port:cc_port1|c_inbuf[4]                         ; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[4] ; a1         ; a1       ; None                        ; None                      ; 4.300 ns                ;
; N/A   ; 43.10 MHz ( period = 23.200 ns ) ; bb_port:bb_port1|b_inbuf[5]                         ; inter_bus:inter_bus1|data_bus_buf:a_bus1|d_inbuf[5] ; a1         ; a1       ; None                        ; None                      ; 5.800 ns                ;