_primary.vhd

用Verilog实现8255芯片功能

library verilog;
use verilog.vl_types.all;
entity r_w_con is
    port(
        rst_n           : in     vl_logic;
        cs_n            : in     vl_logic;
        a0              : in     vl_logic;
        a1              : in     vl_logic;
        wr_n            : in     vl_logic;
        rd_n            : in     vl_logic;
        d_inbuf         : in     vl_logic_vector(7 downto 0);
        lk_bus          : out    vl_logic;
        bus_con         : out    vl_logic_vector(3 downto 0);
        r_w             : out    vl_logic;
        c_port          : out    vl_logic;
        c_upper_io      : out    vl_logic;
        c_lower_io      : out    vl_logic;
        c_set_rst       : out    vl_logic_vector(4 downto 0);
        b_mode_io       : out    vl_logic;
        b_port          : out    vl_logic;
        a_mode_io       : out    vl_logic;
        a_port          : out    vl_logic
    );
end r_w_con;