_primary.vhd

来自「用Verilog实现8255芯片功能」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity inter_bus is
    port(
        bus_con         : in     vl_logic_vector(3 downto 0);
        d_inbuf         : in     vl_logic_vector(7 downto 0);
        d_outbuf        : out    vl_logic_vector(7 downto 0);
        a_outbuf        : out    vl_logic_vector(7 downto 0);
        a_inbuf         : in     vl_logic_vector(7 downto 0);
        b_outbuf        : out    vl_logic_vector(7 downto 0);
        b_inbuf         : in     vl_logic_vector(7 downto 0);
        c_outbuf        : out    vl_logic_vector(7 downto 0);
        c_inbuf         : in     vl_logic_vector(7 downto 0)
    );
end inter_bus;