📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity top_8255 is port( rst_n : in vl_logic; cs_n : in vl_logic; a1 : in vl_logic; a0 : in vl_logic; wr_n : in vl_logic; rd_n : in vl_logic; data_bus : inout vl_logic_vector(7 downto 0); a_bus : inout vl_logic_vector(7 downto 0); b_bus : inout vl_logic_vector(7 downto 0); c_bus : inout vl_logic_vector(7 downto 0) );end top_8255;
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