cc_port.fit.summary

来自「用Verilog实现8255芯片功能」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Thu Nov 09 21:41:43 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : cc_port
Top-level Entity Name : cc_port
Family : ACEX1K
Device : EP1K10TC144-3
Timing Models : Final
Total logic elements : 49 / 576 ( 9 % )
Total pins : 42 / 92 ( 46 % )
Total memory bits : 0 / 12,288 ( 0 % )
Total PLLs : 0