cc_port.map.qmsg

用Verilog实现8255芯片功能

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(96) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(96): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 96 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(96) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(96): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 96 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(97) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(97): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 97 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(97) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(97): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 97 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_outbuf cc_port.v(100) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(100): variable \"c_outbuf\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 100 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_GENERIC_WARNING_WITH_LOC" "overlapping case item expressions are non-constant or contain don't care bits - unable to check case statement for completeness cc_port.v(89) " "Warning (10005): Verilog HDL or VHDL warning at cc_port.v(89): overlapping case item expressions are non-constant or contain don't care bits - unable to check case statement for completeness" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10005 "Verilog HDL or VHDL warning at %2!s!: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_out cc_port.v(81) " "Warning (10240): Verilog HDL Always Construct warning at cc_port.v(81): inferring latch(es) for variable \"c_out\", which holds its previous value in one or more paths through the always construct" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 81 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[7\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[7\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[6\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[6\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[5\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[5\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[4\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[4\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[3\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[3\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[2\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[2\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[1\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[1\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_out\[0\] cc_port.v(89) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for \"c_out\[0\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[0\] " "Warning: Latch c_out\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[1\] " "Warning: Latch c_out\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[2\] " "Warning: Latch c_out\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[3\] " "Warning: Latch c_out\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[4\] " "Warning: Latch c_out\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[5\] " "Warning: Latch c_out\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[6\] " "Warning: Latch c_out\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "c_out\[7\] " "Warning: Latch c_out\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA c_set_rst\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst\[4\]" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "91 " "Info: Implemented 91 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "49 " "Info: Implemented 49 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 37 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 37 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 09 21:41:39 2006 " "Info: Processing ended: Thu Nov 09 21:41:39 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}