cc_port.map.qmsg

用Verilog实现8255芯片功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 09 21:41:38 2006 " "Info: Processing started: Thu Nov 09 21:41:38 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cc_port -c cc_port " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cc_port -c cc_port" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cc_port.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cc_port.v" { { "Info" "ISGN_ENTITY_NAME" "1 cc_port " "Info: Found entity 1: cc_port" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cc_port " "Info: Elaborating entity \"cc_port\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_inbuf cc_port.v(38) " "Warning (10240): Verilog HDL Always Construct warning at cc_port.v(38): inferring latch(es) for variable \"c_inbuf\", which holds its previous value in one or more paths through the always construct" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 38 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[3\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[3\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[2\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[2\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[1\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[1\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[0\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[0\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c_inbuf cc_port.v(48) " "Warning (10240): Verilog HDL Always Construct warning at cc_port.v(48): inferring latch(es) for variable \"c_inbuf\", which holds its previous value in one or more paths through the always construct" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 48 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[7\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[7\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[6\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[6\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[5\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[5\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "c_inbuf\[4\] cc_port.v(26) " "Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for \"c_inbuf\[4\]\"" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(90) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(90): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 90 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(90) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(90): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 90 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(91) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(91): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 91 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(91) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(91): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 91 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(92) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(92): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 92 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(92) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(92): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 92 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(93) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(93): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 93 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(93) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(93): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 93 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(94) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(94): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 94 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(94) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(94): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 94 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_out cc_port.v(95) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(95): variable \"c_out\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 95 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "c_set_rst cc_port.v(95) " "Warning (10235): Verilog HDL Always Construct warning at cc_port.v(95): variable \"c_set_rst\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 95 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}