cc_port.tan.qmsg

用Verilog实现8255芯片功能

{ "Info" "ITDB_FULL_TPD_RESULT" "c_set_rst\[2\] select\[3\] 19.300 ns Longest " "Info: Longest tpd from source pin \"c_set_rst\[2\]\" to destination pin \"select\[3\]\" is 19.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns c_set_rst\[2\] 1 CLK PIN_143 13 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_143; Fanout = 13; CLK Node = 'c_set_rst\[2\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_set_rst[2] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.600 ns) 8.400 ns Decoder0~333 2 COMB LC1_C13 2 " "Info: 2: + IC(1.900 ns) + CELL(1.600 ns) = 8.400 ns; Loc. = LC1_C13; Fanout = 2; COMB Node = 'Decoder0~333'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { c_set_rst[2] Decoder0~333 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.600 ns) 11.800 ns select~191 3 COMB LC8_A22 1 " "Info: 3: + IC(1.800 ns) + CELL(1.600 ns) = 11.800 ns; Loc. = LC8_A22; Fanout = 1; COMB Node = 'select~191'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { Decoder0~333 select~191 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(6.300 ns) 19.300 ns select\[3\] 4 PIN PIN_14 0 " "Info: 4: + IC(1.200 ns) + CELL(6.300 ns) = 19.300 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'select\[3\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { select~191 select[3] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.400 ns ( 74.61 % ) " "Info: Total cell delay = 14.400 ns ( 74.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 25.39 % ) " "Info: Total interconnect delay = 4.900 ns ( 25.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "19.300 ns" { c_set_rst[2] Decoder0~333 select~191 select[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "19.300 ns" { c_set_rst[2] c_set_rst[2]~out Decoder0~333 select~191 select[3] } { 0.000ns 0.000ns 1.900ns 1.800ns 1.200ns } { 0.000ns 4.900ns 1.600ns 1.600ns 6.300ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "c_out\[3\] c_set_rst\[4\] c_set_rst\[2\] 8.200 ns register " "Info: th for register \"c_out\[3\]\" (data pin = \"c_set_rst\[4\]\", clock pin = \"c_set_rst\[2\]\") is 8.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "c_set_rst\[2\] destination 13.800 ns + Longest register " "Info: + Longest clock path from clock \"c_set_rst\[2\]\" to destination register is 13.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns c_set_rst\[2\] 1 CLK PIN_143 13 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_143; Fanout = 13; CLK Node = 'c_set_rst\[2\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_set_rst[2] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.600 ns) 8.400 ns Decoder0~333 2 COMB LC1_C13 2 " "Info: 2: + IC(1.900 ns) + CELL(1.600 ns) = 8.400 ns; Loc. = LC1_C13; Fanout = 2; COMB Node = 'Decoder0~333'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { c_set_rst[2] Decoder0~333 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.700 ns) 11.900 ns Selector9~7 3 COMB LC7_A22 1 " "Info: 3: + IC(1.800 ns) + CELL(1.700 ns) = 11.900 ns; Loc. = LC7_A22; Fanout = 1; COMB Node = 'Selector9~7'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { Decoder0~333 Selector9~7 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 13.800 ns c_out\[3\] 4 REG LC6_A22 1 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 13.800 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out\[3\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Selector9~7 c_out[3] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.800 ns ( 71.01 % ) " "Info: Total cell delay = 9.800 ns ( 71.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 28.99 % ) " "Info: Total interconnect delay = 4.000 ns ( 28.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "13.800 ns" { c_set_rst[2] Decoder0~333 Selector9~7 c_out[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "13.800 ns" { c_set_rst[2] c_set_rst[2]~out Decoder0~333 Selector9~7 c_out[3] } { 0.000ns 0.000ns 1.900ns 1.800ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.700ns 1.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns c_set_rst\[4\] 1 CLK PIN_54 25 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 25; CLK Node = 'c_set_rst\[4\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_set_rst[4] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 3.600 ns Selector8~10 2 COMB LC5_A22 1 " "Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC5_A22; Fanout = 1; COMB Node = 'Selector8~10'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { c_set_rst[4] Selector8~10 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 5.600 ns c_out\[3\] 3 REG LC6_A22 1 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 5.600 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out\[3\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { Selector8~10 c_out[3] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 91.07 % ) " "Info: Total cell delay = 5.100 ns ( 91.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns ( 8.93 % ) " "Info: Total interconnect delay = 0.500 ns ( 8.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { c_set_rst[4] Selector8~10 c_out[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "5.600 ns" { c_set_rst[4] c_set_rst[4]~out Selector8~10 c_out[3] } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.400ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "13.800 ns" { c_set_rst[2] Decoder0~333 Selector9~7 c_out[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "13.800 ns" { c_set_rst[2] c_set_rst[2]~out Decoder0~333 Selector9~7 c_out[3] } { 0.000ns 0.000ns 1.900ns 1.800ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.700ns 1.600ns } } } { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { c_set_rst[4] Selector8~10 c_out[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "5.600 ns" { c_set_rst[4] c_set_rst[4]~out Selector8~10 c_out[3] } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.400ns 1.700ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 19 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 09 21:41:47 2006 " "Info: Processing ended: Thu Nov 09 21:41:47 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}