cc_port.tan.qmsg

用Verilog实现8255芯片功能

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[0\]\$latch " "Warning: Node \"c_inbuf\[0\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[0\] " "Warning: Node \"c_out\[0\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[1\]\$latch " "Warning: Node \"c_inbuf\[1\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[1\] " "Warning: Node \"c_out\[1\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[2\]\$latch " "Warning: Node \"c_inbuf\[2\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[2\] " "Warning: Node \"c_out\[2\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[3\]\$latch " "Warning: Node \"c_inbuf\[3\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[3\] " "Warning: Node \"c_out\[3\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[4\]\$latch " "Warning: Node \"c_inbuf\[4\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[4\] " "Warning: Node \"c_out\[4\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[5\]\$latch " "Warning: Node \"c_inbuf\[5\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[5\] " "Warning: Node \"c_out\[5\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[6\]\$latch " "Warning: Node \"c_inbuf\[6\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[6\] " "Warning: Node \"c_out\[6\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_inbuf\[7\]\$latch " "Warning: Node \"c_inbuf\[7\]\$latch\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c_out\[7\] " "Warning: Node \"c_out\[7\]\" is a latch" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "c_lower_io " "Info: Assuming node \"c_lower_io\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 22 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "c_set_rst\[4\] " "Info: Assuming node \"c_set_rst\[4\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "c_port " "Info: Assuming node \"c_port\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 22 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "r_w " "Info: Assuming node \"r_w\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 22 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "c_set_rst\[2\] " "Info: Assuming node \"c_set_rst\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "c_set_rst\[1\] " "Info: Assuming node \"c_set_rst\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "c_set_rst\[3\] " "Info: Assuming node \"c_set_rst\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "c_upper_io " "Info: Assuming node \"c_upper_io\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 22 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "16 " "Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Selector1~7 " "Info: Detected gated clock \"Selector1~7\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector1~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~338 " "Info: Detected gated clock \"Decoder0~338\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~338" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector3~7 " "Info: Detected gated clock \"Selector3~7\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector3~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~337 " "Info: Detected gated clock \"Decoder0~337\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~337" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector5~7 " "Info: Detected gated clock \"Selector5~7\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector5~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~336 " "Info: Detected gated clock \"Decoder0~336\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~336" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector7~7 " "Info: Detected gated clock \"Selector7~7\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector7~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~335 " "Info: Detected gated clock \"Decoder0~335\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~335" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector9~7 " "Info: Detected gated clock \"Selector9~7\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector9~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector11~7 " "Info: Detected gated clock \"Selector11~7\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector11~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~334 " "Info: Detected gated clock \"Decoder0~334\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~334" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector13~7 " "Info: Detected gated clock \"Selector13~7\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector13~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Selector15~92 " "Info: Detected gated clock \"Selector15~92\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Selector15~92" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~333 " "Info: Detected gated clock \"Decoder0~333\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~333" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~332 " "Info: Detected gated clock \"Decoder0~332\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~332" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Decoder0~331 " "Info: Detected gated clock \"Decoder0~331\" as buffer" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } } { "d:/eda/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/eda/quartus60/win/Assignment Editor.qase" 1 { { 0 "Decoder0~331" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_TSU_RESULT" "c_inbuf\[0\]\$latch c_bus\[0\] c_lower_io 9.000 ns register " "Info: tsu for register \"c_inbuf\[0\]\$latch\" (data pin = \"c_bus\[0\]\", clock pin = \"c_lower_io\") is 9.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.300 ns + Longest pin register " "Info: + Longest pin to register delay is 9.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c_bus\[0\] 1 PIN PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'c_bus\[0\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_bus[0] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns c_bus\[0\]~7 2 COMB IOC_17 1 " "Info: 2: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = IOC_17; Fanout = 1; COMB Node = 'c_bus\[0\]~7'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "4.900 ns" { c_bus[0] c_bus[0]~7 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.700 ns) 9.300 ns c_inbuf\[0\]\$latch 3 REG LC5_C21 1 " "Info: 3: + IC(2.700 ns) + CELL(1.700 ns) = 9.300 ns; Loc. = LC5_C21; Fanout = 1; REG Node = 'c_inbuf\[0\]\$latch'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { c_bus[0]~7 c_inbuf[0]$latch } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns ( 70.97 % ) " "Info: Total cell delay = 6.600 ns ( 70.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 29.03 % ) " "Info: Total interconnect delay = 2.700 ns ( 29.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "9.300 ns" { c_bus[0] c_bus[0]~7 c_inbuf[0]$latch } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "9.300 ns" { c_bus[0] c_bus[0]~7 c_inbuf[0]$latch } { 0.000ns 0.000ns 2.700ns } { 0.000ns 4.900ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.500 ns + " "Info: + Micro setup delay of destination is 3.500 ns" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "c_lower_io destination 3.800 ns - Shortest register " "Info: - Shortest clock path from clock \"c_lower_io\" to destination register is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns c_lower_io 1 CLK PIN_126 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 8; CLK Node = 'c_lower_io'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_lower_io } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 3.800 ns c_inbuf\[0\]\$latch 2 REG LC5_C21 1 " "Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC5_C21; Fanout = 1; REG Node = 'c_inbuf\[0\]\$latch'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { c_lower_io c_inbuf[0]$latch } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 94.74 % ) " "Info: Total cell delay = 3.600 ns ( 94.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 5.26 % ) " "Info: Total interconnect delay = 0.200 ns ( 5.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { c_lower_io c_inbuf[0]$latch } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "3.800 ns" { c_lower_io c_lower_io~out c_inbuf[0]$latch } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "9.300 ns" { c_bus[0] c_bus[0]~7 c_inbuf[0]$latch } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "9.300 ns" { c_bus[0] c_bus[0]~7 c_inbuf[0]$latch } { 0.000ns 0.000ns 2.700ns } { 0.000ns 4.900ns 1.700ns } } } { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { c_lower_io c_inbuf[0]$latch } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "3.800 ns" { c_lower_io c_lower_io~out c_inbuf[0]$latch } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.600ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "c_set_rst\[2\] c_bus\[3\] c_out\[3\] 21.300 ns register " "Info: tco from clock \"c_set_rst\[2\]\" to destination pin \"c_bus\[3\]\" through register \"c_out\[3\]\" is 21.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "c_set_rst\[2\] source 13.800 ns + Longest register " "Info: + Longest clock path from clock \"c_set_rst\[2\]\" to source register is 13.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns c_set_rst\[2\] 1 CLK PIN_143 13 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_143; Fanout = 13; CLK Node = 'c_set_rst\[2\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_set_rst[2] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.600 ns) 8.400 ns Decoder0~333 2 COMB LC1_C13 2 " "Info: 2: + IC(1.900 ns) + CELL(1.600 ns) = 8.400 ns; Loc. = LC1_C13; Fanout = 2; COMB Node = 'Decoder0~333'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { c_set_rst[2] Decoder0~333 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.700 ns) 11.900 ns Selector9~7 3 COMB LC7_A22 1 " "Info: 3: + IC(1.800 ns) + CELL(1.700 ns) = 11.900 ns; Loc. = LC7_A22; Fanout = 1; COMB Node = 'Selector9~7'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { Decoder0~333 Selector9~7 } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 13.800 ns c_out\[3\] 4 REG LC6_A22 1 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 13.800 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out\[3\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Selector9~7 c_out[3] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.800 ns ( 71.01 % ) " "Info: Total cell delay = 9.800 ns ( 71.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 28.99 % ) " "Info: Total interconnect delay = 4.000 ns ( 28.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "13.800 ns" { c_set_rst[2] Decoder0~333 Selector9~7 c_out[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "13.800 ns" { c_set_rst[2] c_set_rst[2]~out Decoder0~333 Selector9~7 c_out[3] } { 0.000ns 0.000ns 1.900ns 1.800ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.700ns 1.600ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.500 ns + Longest register pin " "Info: + Longest register to pin delay is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c_out\[3\] 1 REG LC6_A22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out\[3\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "" { c_out[3] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 89 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(6.300 ns) 7.500 ns c_bus\[3\] 2 PIN PIN_13 0 " "Info: 2: + IC(1.200 ns) + CELL(6.300 ns) = 7.500 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'c_bus\[3\]'" {  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { c_out[3] c_bus[3] } "NODE_NAME" } } { "cc_port.v" "" { Text "F:/cfm/8255-quantus/cc_port/cc_port.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 84.00 % ) " "Info: Total cell delay = 6.300 ns ( 84.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 16.00 % ) " "Info: Total interconnect delay = 1.200 ns ( 16.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { c_out[3] c_bus[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { c_out[3] c_bus[3] } { 0.000ns 1.200ns } { 0.000ns 6.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "13.800 ns" { c_set_rst[2] Decoder0~333 Selector9~7 c_out[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "13.800 ns" { c_set_rst[2] c_set_rst[2]~out Decoder0~333 Selector9~7 c_out[3] } { 0.000ns 0.000ns 1.900ns 1.800ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.700ns 1.600ns } } } { "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { c_out[3] c_bus[3] } "NODE_NAME" } } { "d:/eda/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { c_out[3] c_bus[3] } { 0.000ns 1.200ns } { 0.000ns 6.300ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}