cc_port.tan.rpt

用Verilog实现8255芯片功能

; N/A           ; None        ; -1.800 ns ; c_set_rst[0] ; c_out[1]         ; c_set_rst[3] ;
; N/A           ; None        ; -1.800 ns ; c_set_rst[0] ; c_out[1]         ; c_set_rst[1] ;
; N/A           ; None        ; -1.900 ns ; c_outbuf[1]  ; c_out[1]         ; c_set_rst[3] ;
; N/A           ; None        ; -1.900 ns ; c_outbuf[1]  ; c_out[1]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.300 ns ; c_set_rst[0] ; c_out[7]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.400 ns ; c_outbuf[7]  ; c_out[7]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.400 ns ; c_set_rst[0] ; c_out[4]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.400 ns ; c_set_rst[0] ; c_out[4]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.400 ns ; c_set_rst[0] ; c_out[4]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.400 ns ; c_set_rst[0] ; c_out[5]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.500 ns ; c_outbuf[5]  ; c_out[5]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.500 ns ; c_outbuf[4]  ; c_out[4]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.500 ns ; c_outbuf[4]  ; c_out[4]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.500 ns ; c_outbuf[4]  ; c_out[4]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.500 ns ; c_set_rst[0] ; c_out[2]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.500 ns ; c_set_rst[0] ; c_out[2]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.500 ns ; c_set_rst[0] ; c_out[5]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.500 ns ; c_set_rst[0] ; c_out[5]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.500 ns ; c_set_rst[0] ; c_out[6]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.500 ns ; c_set_rst[0] ; c_out[6]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.500 ns ; c_set_rst[0] ; c_out[7]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.600 ns ; c_outbuf[7]  ; c_out[7]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.600 ns ; c_outbuf[6]  ; c_out[6]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.600 ns ; c_outbuf[6]  ; c_out[6]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.600 ns ; c_outbuf[5]  ; c_out[5]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.600 ns ; c_outbuf[5]  ; c_out[5]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.600 ns ; c_set_rst[0] ; c_out[7]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.700 ns ; c_outbuf[7]  ; c_out[7]         ; c_set_rst[3] ;
; N/A           ; None        ; -2.700 ns ; c_set_rst[0] ; c_out[2]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.700 ns ; c_set_rst[0] ; c_out[6]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.800 ns ; c_outbuf[6]  ; c_out[6]         ; c_set_rst[1] ;
; N/A           ; None        ; -2.800 ns ; c_outbuf[2]  ; c_out[2]         ; c_set_rst[4] ;
; N/A           ; None        ; -2.800 ns ; c_outbuf[2]  ; c_out[2]         ; c_set_rst[3] ;
; N/A           ; None        ; -3.000 ns ; c_outbuf[2]  ; c_out[2]         ; c_set_rst[1] ;
; N/A           ; None        ; -4.000 ns ; c_bus[7]     ; c_inbuf[7]$latch ; c_upper_io   ;
; N/A           ; None        ; -4.000 ns ; c_bus[6]     ; c_inbuf[6]$latch ; c_upper_io   ;
; N/A           ; None        ; -4.000 ns ; c_bus[5]     ; c_inbuf[5]$latch ; c_upper_io   ;
; N/A           ; None        ; -4.000 ns ; c_bus[4]     ; c_inbuf[4]$latch ; c_upper_io   ;
; N/A           ; None        ; -4.000 ns ; c_bus[3]     ; c_inbuf[3]$latch ; c_lower_io   ;
; N/A           ; None        ; -4.000 ns ; c_bus[1]     ; c_inbuf[1]$latch ; c_lower_io   ;
; N/A           ; None        ; -4.100 ns ; c_bus[2]     ; c_inbuf[2]$latch ; c_lower_io   ;
; N/A           ; None        ; -4.100 ns ; c_outbuf[3]  ; c_out[3]         ; c_set_rst[4] ;
; N/A           ; None        ; -4.700 ns ; c_set_rst[0] ; c_out[3]         ; c_set_rst[4] ;
; N/A           ; None        ; -5.000 ns ; c_set_rst[0] ; c_out[0]         ; c_set_rst[4] ;
; N/A           ; None        ; -5.000 ns ; c_set_rst[0] ; c_out[1]         ; c_set_rst[4] ;
; N/A           ; None        ; -5.100 ns ; c_outbuf[1]  ; c_out[1]         ; c_set_rst[4] ;
; N/A           ; None        ; -5.100 ns ; c_outbuf[0]  ; c_out[0]         ; c_set_rst[4] ;
; N/A           ; None        ; -5.500 ns ; c_bus[0]     ; c_inbuf[0]$latch ; c_lower_io   ;
+---------------+-------------+-----------+--------------+------------------+--------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Nov 09 21:41:46 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cc_port -c cc_port
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "c_inbuf[0]$latch" is a latch
    Warning: Node "c_out[0]" is a latch
    Warning: Node "c_inbuf[1]$latch" is a latch
    Warning: Node "c_out[1]" is a latch
    Warning: Node "c_inbuf[2]$latch" is a latch
    Warning: Node "c_out[2]" is a latch
    Warning: Node "c_inbuf[3]$latch" is a latch
    Warning: Node "c_out[3]" is a latch
    Warning: Node "c_inbuf[4]$latch" is a latch
    Warning: Node "c_out[4]" is a latch
    Warning: Node "c_inbuf[5]$latch" is a latch
    Warning: Node "c_out[5]" is a latch
    Warning: Node "c_inbuf[6]$latch" is a latch
    Warning: Node "c_out[6]" is a latch
    Warning: Node "c_inbuf[7]$latch" is a latch
    Warning: Node "c_out[7]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "c_lower_io" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "c_set_rst[4]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "c_port" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "r_w" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "c_set_rst[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "c_set_rst[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "c_set_rst[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "c_upper_io" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Selector1~7" as buffer
    Info: Detected gated clock "Decoder0~338" as buffer
    Info: Detected gated clock "Selector3~7" as buffer
    Info: Detected gated clock "Decoder0~337" as buffer
    Info: Detected gated clock "Selector5~7" as buffer
    Info: Detected gated clock "Decoder0~336" as buffer
    Info: Detected gated clock "Selector7~7" as buffer
    Info: Detected gated clock "Decoder0~335" as buffer
    Info: Detected gated clock "Selector9~7" as buffer
    Info: Detected gated clock "Selector11~7" as buffer
    Info: Detected gated clock "Decoder0~334" as buffer
    Info: Detected gated clock "Selector13~7" as buffer
    Info: Detected gated clock "Selector15~92" as buffer
    Info: Detected gated clock "Decoder0~333" as buffer
    Info: Detected gated clock "Decoder0~332" as buffer
    Info: Detected gated clock "Decoder0~331" as buffer
Info: tsu for register "c_inbuf[0]$latch" (data pin = "c_bus[0]", clock pin = "c_lower_io") is 9.000 ns
    Info: + Longest pin to register delay is 9.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'c_bus[0]'
        Info: 2: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = IOC_17; Fanout = 1; COMB Node = 'c_bus[0]~7'
        Info: 3: + IC(2.700 ns) + CELL(1.700 ns) = 9.300 ns; Loc. = LC5_C21; Fanout = 1; REG Node = 'c_inbuf[0]$latch'
        Info: Total cell delay = 6.600 ns ( 70.97 % )
        Info: Total interconnect delay = 2.700 ns ( 29.03 % )
    Info: + Micro setup delay of destination is 3.500 ns
    Info: - Shortest clock path from clock "c_lower_io" to destination register is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 8; CLK Node = 'c_lower_io'
        Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC5_C21; Fanout = 1; REG Node = 'c_inbuf[0]$latch'
        Info: Total cell delay = 3.600 ns ( 94.74 % )
        Info: Total interconnect delay = 0.200 ns ( 5.26 % )
Info: tco from clock "c_set_rst[2]" to destination pin "c_bus[3]" through register "c_out[3]" is 21.300 ns
    Info: + Longest clock path from clock "c_set_rst[2]" to source register is 13.800 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_143; Fanout = 13; CLK Node = 'c_set_rst[2]'
        Info: 2: + IC(1.900 ns) + CELL(1.600 ns) = 8.400 ns; Loc. = LC1_C13; Fanout = 2; COMB Node = 'Decoder0~333'
        Info: 3: + IC(1.800 ns) + CELL(1.700 ns) = 11.900 ns; Loc. = LC7_A22; Fanout = 1; COMB Node = 'Selector9~7'
        Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 13.800 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out[3]'
        Info: Total cell delay = 9.800 ns ( 71.01 % )
        Info: Total interconnect delay = 4.000 ns ( 28.99 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out[3]'
        Info: 2: + IC(1.200 ns) + CELL(6.300 ns) = 7.500 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'c_bus[3]'
        Info: Total cell delay = 6.300 ns ( 84.00 % )
        Info: Total interconnect delay = 1.200 ns ( 16.00 % )
Info: Longest tpd from source pin "c_set_rst[2]" to destination pin "select[3]" is 19.300 ns
    Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_143; Fanout = 13; CLK Node = 'c_set_rst[2]'
    Info: 2: + IC(1.900 ns) + CELL(1.600 ns) = 8.400 ns; Loc. = LC1_C13; Fanout = 2; COMB Node = 'Decoder0~333'
    Info: 3: + IC(1.800 ns) + CELL(1.600 ns) = 11.800 ns; Loc. = LC8_A22; Fanout = 1; COMB Node = 'select~191'
    Info: 4: + IC(1.200 ns) + CELL(6.300 ns) = 19.300 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'select[3]'
    Info: Total cell delay = 14.400 ns ( 74.61 % )
    Info: Total interconnect delay = 4.900 ns ( 25.39 % )
Info: th for register "c_out[3]" (data pin = "c_set_rst[4]", clock pin = "c_set_rst[2]") is 8.200 ns
    Info: + Longest clock path from clock "c_set_rst[2]" to destination register is 13.800 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_143; Fanout = 13; CLK Node = 'c_set_rst[2]'
        Info: 2: + IC(1.900 ns) + CELL(1.600 ns) = 8.400 ns; Loc. = LC1_C13; Fanout = 2; COMB Node = 'Decoder0~333'
        Info: 3: + IC(1.800 ns) + CELL(1.700 ns) = 11.900 ns; Loc. = LC7_A22; Fanout = 1; COMB Node = 'Selector9~7'
        Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 13.800 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out[3]'
        Info: Total cell delay = 9.800 ns ( 71.01 % )
        Info: Total interconnect delay = 4.000 ns ( 28.99 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 25; CLK Node = 'c_set_rst[4]'
        Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC5_A22; Fanout = 1; COMB Node = 'Selector8~10'
        Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 5.600 ns; Loc. = LC6_A22; Fanout = 1; REG Node = 'c_out[3]'
        Info: Total cell delay = 5.100 ns ( 91.07 % )
        Info: Total interconnect delay = 0.500 ns ( 8.93 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 19 warnings
    Info: Processing ended: Thu Nov 09 21:41:47 2006
    Info: Elapsed time: 00:00:01