cc_port.tan.summary

用Verilog实现8255芯片功能

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.000 ns
From           : c_bus[0]
To             : c_inbuf[0]$latch
From Clock     : --
To Clock       : c_lower_io
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.300 ns
From           : c_out[3]
To             : c_bus[3]
From Clock     : c_set_rst[2]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 19.300 ns
From           : c_set_rst[2]
To             : select[3]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 8.200 ns
From           : c_set_rst[4]
To             : c_out[3]
From Clock     : --
To Clock       : c_set_rst[2]
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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