cc_port.map.rpt

用Verilog实现8255芯片功能

+---------------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |cc_port                   ; 49 (49)     ; 0            ; 0           ; 42   ; 49 (49)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |cc_port            ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; c_inbuf[0]$latch                                    ; c_lower_io          ; yes                    ;
; c_inbuf[1]$latch                                    ; c_lower_io          ; yes                    ;
; c_inbuf[2]$latch                                    ; c_lower_io          ; yes                    ;
; c_inbuf[3]$latch                                    ; c_lower_io          ; yes                    ;
; c_inbuf[4]$latch                                    ; c_upper_io          ; yes                    ;
; c_inbuf[5]$latch                                    ; c_upper_io          ; yes                    ;
; c_inbuf[6]$latch                                    ; c_upper_io          ; yes                    ;
; c_inbuf[7]$latch                                    ; c_upper_io          ; yes                    ;
; c_out[0]                                            ; Selector15          ; yes                    ;
; c_out[1]                                            ; Selector13          ; yes                    ;
; c_out[2]                                            ; Selector11          ; yes                    ;
; c_out[3]                                            ; Selector9           ; yes                    ;
; c_out[4]                                            ; Selector7           ; yes                    ;
; c_out[5]                                            ; Selector5           ; yes                    ;
; c_out[6]                                            ; Selector3           ; yes                    ;
; c_out[7]                                            ; Selector1           ; yes                    ;
; Number of user-specified and inferred latches = 16  ;                     ;                        ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Nov 09 21:41:38 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cc_port -c cc_port
Info: Found 1 design units, including 1 entities, in source file cc_port.v
    Info: Found entity 1: cc_port
Info: Elaborating entity "cc_port" for the top level hierarchy
Warning (10240): Verilog HDL Always Construct warning at cc_port.v(38): inferring latch(es) for variable "c_inbuf", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[3]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[2]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[1]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[0]"
Warning (10240): Verilog HDL Always Construct warning at cc_port.v(48): inferring latch(es) for variable "c_inbuf", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[7]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[6]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[5]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(26): inferred latch for "c_inbuf[4]"
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(90): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(90): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(91): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(91): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(92): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(92): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(93): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(93): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(94): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(94): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(95): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(95): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(96): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(96): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(97): variable "c_set_rst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(97): variable "c_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at cc_port.v(100): variable "c_outbuf" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10005): Verilog HDL or VHDL warning at cc_port.v(89): overlapping case item expressions are non-constant or contain don't care bits - unable to check case statement for completeness
Warning (10240): Verilog HDL Always Construct warning at cc_port.v(81): inferring latch(es) for variable "c_out", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[7]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[6]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[5]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[4]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[3]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[2]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[1]"
Info (10041): Verilog HDL or VHDL info at cc_port.v(89): inferred latch for "c_out[0]"
Warning: Latch c_out[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Warning: Latch c_out[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Warning: Latch c_out[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Warning: Latch c_out[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Warning: Latch c_out[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Warning: Latch c_out[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Warning: Latch c_out[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Warning: Latch c_out[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal c_set_rst[4]
Info: Implemented 91 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 16 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 49 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 37 warnings
    Info: Processing ended: Thu Nov 09 21:41:39 2006
    Info: Elapsed time: 00:00:01