bcm5700-7.4.11-2.6.8.1.patch

网络编程,关于网卡驱动方面的资料.

+		{ 0x2478, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x2480, 0x0000, 0xffffffff, 0x00000000 },
+		{ 0x2484, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x2488, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x248c, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x2490, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x2494, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x2498, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x249c, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24a0, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24a4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24a8, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24ac, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24b0, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24b4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24b8, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24bc, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x24c0, 0x0000, 0xffffffff, 0x00000000 },
+	
+		/* Receive Data Completion Control Registers */
+		{ 0x2800, 0x0000, 0x00000000, 0x00000002 },
+
+		/* Receive BD Initiator Control Registers. */
+		{ 0x2c00, 0x0000, 0x00000000, 0x00000006 },
+		{ 0x2c04, 0x0000, 0x00000004, 0x00000000 },
+		{ 0x2c18, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x2c18, 0x0001, 0x00000000, 0x000003ff },	/* 5705 */
+		{ 0x2c1c, 0x0002, 0x00000000, 0xffffffff },
+	
+		/* Receive BD Completion Control Registers. */
+		{ 0x3000, 0x0000, 0x00000000, 0x00000006 },
+		{ 0x3004, 0x0000, 0x00000004, 0x00000000 },
+		{ 0x3008, 0x0002, 0x00000000, 0x000000ff },
+		{ 0x300c, 0x0000, 0x00000000, 0x000001ff },
+
+		/* Host Coalescing Control Registers. */
+		{ 0x3c00, 0x0002, 0x00000000, 0x00000004 },
+		{ 0x3c00, 0x0001, 0x00000000, 0x000000f6 },	/* 5705 */
+		{ 0x3c04, 0x0000, 0x00000004, 0x00000000 },
+		{ 0x3c08, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c08, 0x0001, 0x00000000, 0x000003ff },	/* 5705 */
+		{ 0x3c0c, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c0c, 0x0001, 0x00000000, 0x000003ff },	/* 5705 */
+		{ 0x3c10, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c10, 0x0005, 0x00000000, 0x000000ff },	/* 5705 */
+		{ 0x3c14, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c14, 0x0005, 0x00000000, 0x000000ff },	/* 5705 */
+		{ 0x3c18, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c1c, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c20, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c20, 0x0005, 0x00000000, 0x000000ff },	/* 5705 */
+		{ 0x3c24, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c24, 0x0005, 0x00000000, 0x000000ff },	/* 5705 */
+		{ 0x3c28, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c30, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c34, 0x0002, 0x00000000, 0xffffffff },
+		{ 0x3c38, 0x0000, 0x00000000, 0xffffffff },
+		{ 0x3c3c, 0x0000, 0x00000000, 0xffffffff },
+		{ 0x3c40, 0x0000, 0xffffffff, 0x00000000 },
+		{ 0x3c44, 0x0000, 0xffffffff, 0x00000000 },
+		{ 0x3c50, 0x0002, 0x00000000, 0x000000ff },
+		{ 0x3c54, 0x0000, 0x00000000, 0x000000ff },
+		{ 0x3c80, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3c80, 0x0001, 0x00000000, 0x000001ff },	/* 5705 */
+		{ 0x3c84, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3c88, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3c8c, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3c90, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3c94, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3c98, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3c9c, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3ca0, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3ca4, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3ca8, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3cac, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3cb0, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3cb4, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3cb8, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3cbc, 0x0002, 0x00000000, 0x000007ff },
+		{ 0x3cc0, 0x0000, 0x00000000, 0x000001ff },
+		{ 0x3cc4, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cc8, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3ccc, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cd0, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cd4, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cd8, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cdc, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3ce0, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3ce4, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3ce8, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cec, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cf0, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cf4, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cf8, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x3cfc, 0x0002, 0x00000000, 0x000001ff },
+
+		/* Memory Arbiter Registers */
+		{ 0x4000, 0x0002, 0x00000000, 0x001ffffe },
+		{ 0x4000, 0x0001, 0x00000000, 0x38111e7e },
+		{ 0x4004, 0x0002, 0x001ffffc, 0x00000000 },
+		{ 0x4004, 0x0002, 0x00111dfc, 0x00000000 },
+		{ 0x4008, 0x0000, 0x00000000, 0x001fffff },
+		{ 0x400c, 0x0000, 0x00000000, 0x001fffff },
+
+		/* Buffer Manager Control Registers. */
+		{ 0x4400, 0x0000, 0x00000000, 0x0000001c },
+		{ 0x4404, 0x0000, 0x00000014, 0x00000000 },
+		{ 0x4408, 0x0000, 0x00000000, 0x007fff80 },
+		{ 0x440c, 0x0000, 0x00000000, 0x007fffff },
+		{ 0x4410, 0x0000, 0x00000000, 0x0000003f },
+		{ 0x4414, 0x0000, 0x00000000, 0x000001ff },
+		{ 0x4418, 0x0000, 0x00000000, 0x000001ff },
+		{ 0x4420, 0x0000, 0xffffffff, 0x00000000 },
+		{ 0x4428, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x442c, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x4430, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x4440, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x4448, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x444c, 0x0000, 0xffffffff, 0x00000000 },
+		{ 0x4450, 0x0000, 0xffffffff, 0x00000000 },
+		{ 0x4454, 0x0000, 0xffffffff, 0x00000000 },
+		{ 0x4458, 0x0001, 0x00000000, 0x000001ff },	/* 5705 */
+	
+		{ 0x4800, 0x0002, 0x00000000, 0x000003fe },
+		{ 0x4800, 0x0001, 0x00000000, 0xc00003fe },	/* 5705 */
+		{ 0x4804, 0x0000, 0x000003fc, 0x00000000 },
+		{ 0x4c00, 0x0002, 0x00000000, 0x000003fc },
+		{ 0x4c00, 0x0001, 0x00000000, 0x000007fc },	/* 5705 */
+		{ 0x4c04, 0x0000, 0x000003fc, 0x00000000 },
+
+		/* Mailbox Registers */
+		{ 0x5804, 0x0000, 0x00000000, 0xffffffff },
+		{ 0x586c, 0x0000, 0x00000000, 0x000001ff },
+		{ 0x5874, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x5884, 0x0000, 0x00000000, 0x000007ff },
+		{ 0x5904, 0x0000, 0x00000000, 0x000001ff },
+		{ 0x5984, 0x0002, 0x00000000, 0x000001ff },
+		{ 0x5a04, 0x0000, 0x00000000, 0xffffffff },
+		{ 0x5a0c, 0x0000, 0x00000000, 0xffffffff },
+
+		/* Flow Through Queues. */
+		{ 0x5c14, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c24, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c34, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c44, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c54, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c64, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c74, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c84, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5c94, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5ca4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5cb4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5cc4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5cd4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5ce4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5cf4, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5d04, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0x5d14, 0x0002, 0xffffffff, 0x00000000 },
+		{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
+	};
+
+	if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) {
+		bcm5705 = 1;
+	}
+	else {
+		bcm5705 = 0;
+	}
+
+	ret = 1;
+	for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
+		if (bcm5705 && (reg_tbl[i].flags & NOT_FOR_BCM5705))
+			continue;
+		if (!bcm5705 && (reg_tbl[i].flags & BCM5705_ONLY))
+			continue;
+		if ((pDevice->Flags & BCM5788_FLAG) &&
+			(reg_tbl[i].flags & NOT_FOR_BCM5788))
+			continue;
+		offset = (LM_UINT32) reg_tbl[i].offset;
+		read_mask = reg_tbl[i].read_mask;
+		write_mask = reg_tbl[i].write_mask;
+
+		/* Save the original register content */
+		save_val = LM_RegRd(pDevice, offset);
+
+		/* Determine the read-only value. */
+		read_val = save_val & read_mask;
+
+		/* Write zero to the register, then make sure the read-only bits
+		   are not changed and the read/write bits are all zeros. */
+		LM_RegWr(pDevice, offset, 0, FALSE);
+
+		val = LM_RegRd(pDevice, offset);
+
+		/* Test the read-only and read/write bits. */
+		if (((val & read_mask) != read_val) ||
+			(val & write_mask)) {
+
+	                ret = 0;
+			LM_RegWr(pDevice, offset, save_val, FALSE);
+			break;
+		}
+
+
+		/* Write ones to all the bits defined by RdMask and WrMask, then
+		   make sure the read-only bits are not changed and the
+		   read/write bits are all ones. */
+		LM_RegWr(pDevice, offset, read_mask | write_mask, FALSE);
+
+		val = LM_RegRd(pDevice, offset);
+
+		/* Test the read-only bits. */
+		if ((val & read_mask) != read_val) {
+	                ret = 0;
+			LM_RegWr(pDevice, offset, save_val, FALSE);
+			break;
+		}
+
+		/* Test the read/write bits. */
+		if ((val & write_mask) != write_mask) {
+	                ret = 0;
+			LM_RegWr(pDevice, offset, save_val, FALSE);
+			break;
+		}
+
+		LM_RegWr(pDevice, offset, save_val, FALSE);
+	}
+
+	return ret;
+}
+
+
+/* Returns 1 on success, 0 on failure */
+int
+b57_do_memory_test(LM_DEVICE_BLOCK *pDevice, LM_UINT32 start, LM_UINT32 size)
+{
+	const LM_UINT32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
+		0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
+	LM_UINT32 offset;
+	int i;
+
+	for (i = 0; i < sizeof(test_pattern)/sizeof(LM_UINT32); i++) {
+		for (offset = 0; offset < size; offset += 4) {
+
+			LM_MemWrInd(pDevice, start + offset, test_pattern[i]);
+
+			if (LM_MemRdInd(pDevice, start + offset) !=
+				test_pattern[i]) {
+				return 0;
+			}
+		}
+	}
+	return 1;
+}
+
+/* Returns 1 on success, 0 on failure */
+int
+b57_test_memory(UM_DEVICE_BLOCK *pUmDevice)
+{
+	LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev;
+	int ret = 0;
+	int i;
+	mem_entry_t *mem_tbl;
+
+	static mem_entry_t mem_tbl_570x[] = {
+		{ 0x00000000, 0x01000},
+		{ 0x00002000, 0x1c000},
+		{ 0xffffffff, 0x00000}
+	};
+	static mem_entry_t mem_tbl_5705[] = {
+		{ 0x00000100, 0x0000c},
+		{ 0x00000200, 0x00008},
+		{ 0x00000b50, 0x00400},
+		{ 0x00004000, 0x00800},
+		{ 0x00006000, 0x01000},
+		{ 0x00008000, 0x02000},
+		{ 0x00010000, 0x0e000},
+		{ 0xffffffff, 0x00000}
+	};
+
+	if (T3_ASIC_5705_OR_5750(pDevice->ChipRevId)) {
+		mem_tbl = mem_tbl_5705;
+	}
+	else {
+		mem_tbl = mem_tbl_570x;
+	}
+	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
+		if ((ret = b57_do_memory_test(pDevice, mem_tbl[i].offset,
+			mem_tbl[i].len)) == 0) {
+			return ret;
+		}
+	}
+	
+	return ret;
+}
+
+#define EEPROM_SIZE 0x100
+
+/* Returns 1 on success, 0 on failure */
+int
+b57_test_nvram(UM_DEVICE_BLOCK *pUmDevice)
+{
+	LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev;
+	LM_UINT32 buf[EEPROM_SIZE/4];
+	LM_UINT8 *pdata = (LM_UINT8 *) buf;
+	int i;
+	LM_UINT32 magic, csum;
+
+	for (i = 0; i < EEPROM_SIZE; i += 4) {
+		if (LM_NvramRead(pDevice, i, (LM_UINT32 *) (pdata + i)) !=
+			LM_STATUS_SUCCESS) {
+			break;
+		}
+	}
+	if (i < EEPROM_SIZE) {
+		return 0;
+	}
+
+        magic = MM_SWAP_BE32(buf[0]);
+	if (magic != 0x669955aa) {
+		return 0;
+	}
+
+	csum = ComputeCrc32(pdata, 16);
+	if(csum != MM_SWAP_LE32(buf[0x10/4])) {
+		return 0;
+	}
+
+	csum = ComputeCrc32(&pdata[0x74], 136);
+	if (csum != MM_SWAP_LE32(buf[0xfc/4])) {
+		return 0;
+	}
+
+	return 1;
+}
+
+/* Returns 1 on success, 0 on failure */
+int
+b57_test_link(UM_DEVICE_BLOCK *pUmDevice)
+{
+	LM_DEVICE_BLOCK *pDevice = &pUmDevice->lm_dev;
+	LM_UINT32 phy_reg;
+
+	if (pDevice->TbiFlags & ENABLE_TBI_FLAG) {
+		if (REG_RD(pDevice, MacCtrl.Status) &
+			(MAC_STATUS_PCS_SYNCED | MAC_STATUS_SIGNAL_DETECTED)) {
+			return 1;
+		}
+		return 0;
+	}
+	LM