psocgpioint.h

电容感应程序

#define CSA_1SW1_MASK 0x10
#pragma	ioport	CSA_1SW1_MUXBusCtrl_ADDR:	0x1d9
BYTE			CSA_1SW1_MUXBusCtrl_ADDR;
// CSA_1SW1 Shadow defines
//   CSA_1SW1_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define CSA_1SW1_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSA_1SW2 address and mask defines
#pragma	ioport	CSA_1SW2_Data_ADDR:	0x4
BYTE			CSA_1SW2_Data_ADDR;
#pragma	ioport	CSA_1SW2_DriveMode_0_ADDR:	0x104
BYTE			CSA_1SW2_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW2_DriveMode_1_ADDR:	0x105
BYTE			CSA_1SW2_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW2_IntEn_ADDR:	0x5
BYTE			CSA_1SW2_IntEn_ADDR;
#define CSA_1SW2_MASK 0x40
#pragma	ioport	CSA_1SW2_MUXBusCtrl_ADDR:	0x1d9
BYTE			CSA_1SW2_MUXBusCtrl_ADDR;
// CSA_1SW2 Shadow defines
//   CSA_1SW2_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define CSA_1SW2_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSA_1SW5 address and mask defines
#pragma	ioport	CSA_1SW5_Data_ADDR:	0xc
BYTE			CSA_1SW5_Data_ADDR;
#pragma	ioport	CSA_1SW5_DriveMode_0_ADDR:	0x10c
BYTE			CSA_1SW5_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW5_DriveMode_1_ADDR:	0x10d
BYTE			CSA_1SW5_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW5_IntEn_ADDR:	0xd
BYTE			CSA_1SW5_IntEn_ADDR;
#define CSA_1SW5_MASK 0x1
#pragma	ioport	CSA_1SW5_MUXBusCtrl_ADDR:	0x1db
BYTE			CSA_1SW5_MUXBusCtrl_ADDR;
// CSA_1SW5 Shadow defines
//   CSA_1SW5_DataShadow define
extern unsigned char Port_3_Data_SHADE;
#define CSA_1SW5_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSA_1SW3 address and mask defines
#pragma	ioport	CSA_1SW3_Data_ADDR:	0xc
BYTE			CSA_1SW3_Data_ADDR;
#pragma	ioport	CSA_1SW3_DriveMode_0_ADDR:	0x10c
BYTE			CSA_1SW3_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW3_DriveMode_1_ADDR:	0x10d
BYTE			CSA_1SW3_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW3_IntEn_ADDR:	0xd
BYTE			CSA_1SW3_IntEn_ADDR;
#define CSA_1SW3_MASK 0x4
#pragma	ioport	CSA_1SW3_MUXBusCtrl_ADDR:	0x1db
BYTE			CSA_1SW3_MUXBusCtrl_ADDR;
// CSA_1SW3 Shadow defines
//   CSA_1SW3_DataShadow define
extern unsigned char Port_3_Data_SHADE;
#define CSA_1SW3_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// LCD_1D4 address and mask defines
#pragma	ioport	LCD_1D4_Data_ADDR:	0x8
BYTE			LCD_1D4_Data_ADDR;
#pragma	ioport	LCD_1D4_DriveMode_0_ADDR:	0x108
BYTE			LCD_1D4_DriveMode_0_ADDR;
#pragma	ioport	LCD_1D4_DriveMode_1_ADDR:	0x109
BYTE			LCD_1D4_DriveMode_1_ADDR;
#pragma	ioport	LCD_1D4_IntEn_ADDR:	0x9
BYTE			LCD_1D4_IntEn_ADDR;
#define LCD_1D4_MASK 0x1
#pragma	ioport	LCD_1D4_MUXBusCtrl_ADDR:	0x1da
BYTE			LCD_1D4_MUXBusCtrl_ADDR;
// LCD_1D4 Shadow defines
//   LCD_1D4_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define LCD_1D4_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   LCD_1D4_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define LCD_1D4_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   LCD_1D4_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define LCD_1D4_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// LCD_1D6 address and mask defines
#pragma	ioport	LCD_1D6_Data_ADDR:	0x8
BYTE			LCD_1D6_Data_ADDR;
#pragma	ioport	LCD_1D6_DriveMode_0_ADDR:	0x108
BYTE			LCD_1D6_DriveMode_0_ADDR;
#pragma	ioport	LCD_1D6_DriveMode_1_ADDR:	0x109
BYTE			LCD_1D6_DriveMode_1_ADDR;
#pragma	ioport	LCD_1D6_IntEn_ADDR:	0x9
BYTE			LCD_1D6_IntEn_ADDR;
#define LCD_1D6_MASK 0x4
#pragma	ioport	LCD_1D6_MUXBusCtrl_ADDR:	0x1da
BYTE			LCD_1D6_MUXBusCtrl_ADDR;
// LCD_1D6 Shadow defines
//   LCD_1D6_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define LCD_1D6_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   LCD_1D6_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define LCD_1D6_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   LCD_1D6_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define LCD_1D6_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// LCD_1E address and mask defines
#pragma	ioport	LCD_1E_Data_ADDR:	0x8
BYTE			LCD_1E_Data_ADDR;
#pragma	ioport	LCD_1E_DriveMode_0_ADDR:	0x108
BYTE			LCD_1E_DriveMode_0_ADDR;
#pragma	ioport	LCD_1E_DriveMode_1_ADDR:	0x109
BYTE			LCD_1E_DriveMode_1_ADDR;
#pragma	ioport	LCD_1E_IntEn_ADDR:	0x9
BYTE			LCD_1E_IntEn_ADDR;
#define LCD_1E_MASK 0x10
#pragma	ioport	LCD_1E_MUXBusCtrl_ADDR:	0x1da
BYTE			LCD_1E_MUXBusCtrl_ADDR;
// LCD_1E Shadow defines
//   LCD_1E_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define LCD_1E_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   LCD_1E_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define LCD_1E_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   LCD_1E_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define LCD_1E_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// LCD_1RW address and mask defines
#pragma	ioport	LCD_1RW_Data_ADDR:	0x8
BYTE			LCD_1RW_Data_ADDR;
#pragma	ioport	LCD_1RW_DriveMode_0_ADDR:	0x108
BYTE			LCD_1RW_DriveMode_0_ADDR;
#pragma	ioport	LCD_1RW_DriveMode_1_ADDR:	0x109
BYTE			LCD_1RW_DriveMode_1_ADDR;
#pragma	ioport	LCD_1RW_IntEn_ADDR:	0x9
BYTE			LCD_1RW_IntEn_ADDR;
#define LCD_1RW_MASK 0x40
#pragma	ioport	LCD_1RW_MUXBusCtrl_ADDR:	0x1da
BYTE			LCD_1RW_MUXBusCtrl_ADDR;
// LCD_1RW Shadow defines
//   LCD_1RW_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define LCD_1RW_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   LCD_1RW_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define LCD_1RW_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   LCD_1RW_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define LCD_1RW_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// CSA_1SW7 address and mask defines
#pragma	ioport	CSA_1SW7_Data_ADDR:	0x0
BYTE			CSA_1SW7_Data_ADDR;
#pragma	ioport	CSA_1SW7_DriveMode_0_ADDR:	0x100
BYTE			CSA_1SW7_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW7_DriveMode_1_ADDR:	0x101
BYTE			CSA_1SW7_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW7_IntEn_ADDR:	0x1
BYTE			CSA_1SW7_IntEn_ADDR;
#define CSA_1SW7_MASK 0x1
#pragma	ioport	CSA_1SW7_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSA_1SW7_MUXBusCtrl_ADDR;
// CSA_1SW7 Shadow defines
//   CSA_1SW7_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define CSA_1SW7_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSA_1SW9 address and mask defines
#pragma	ioport	CSA_1SW9_Data_ADDR:	0x0
BYTE			CSA_1SW9_Data_ADDR;
#pragma	ioport	CSA_1SW9_DriveMode_0_ADDR:	0x100
BYTE			CSA_1SW9_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW9_DriveMode_1_ADDR:	0x101
BYTE			CSA_1SW9_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW9_IntEn_ADDR:	0x1
BYTE			CSA_1SW9_IntEn_ADDR;
#define CSA_1SW9_MASK 0x4
#pragma	ioport	CSA_1SW9_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSA_1SW9_MUXBusCtrl_ADDR;
// CSA_1SW9 Shadow defines
//   CSA_1SW9_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define CSA_1SW9_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSA_1SW11 address and mask defines
#pragma	ioport	CSA_1SW11_Data_ADDR:	0x0
BYTE			CSA_1SW11_Data_ADDR;
#pragma	ioport	CSA_1SW11_DriveMode_0_ADDR:	0x100
BYTE			CSA_1SW11_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW11_DriveMode_1_ADDR:	0x101
BYTE			CSA_1SW11_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW11_IntEn_ADDR:	0x1
BYTE			CSA_1SW11_IntEn_ADDR;
#define CSA_1SW11_MASK 0x10
#pragma	ioport	CSA_1SW11_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSA_1SW11_MUXBusCtrl_ADDR;
// CSA_1SW11 Shadow defines
//   CSA_1SW11_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define CSA_1SW11_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSA_1SW13 address and mask defines
#pragma	ioport	CSA_1SW13_Data_ADDR:	0x0
BYTE			CSA_1SW13_Data_ADDR;
#pragma	ioport	CSA_1SW13_DriveMode_0_ADDR:	0x100
BYTE			CSA_1SW13_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW13_DriveMode_1_ADDR:	0x101
BYTE			CSA_1SW13_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW13_IntEn_ADDR:	0x1
BYTE			CSA_1SW13_IntEn_ADDR;
#define CSA_1SW13_MASK 0x40
#pragma	ioport	CSA_1SW13_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSA_1SW13_MUXBusCtrl_ADDR;
// CSA_1SW13 Shadow defines
//   CSA_1SW13_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define CSA_1SW13_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSA_1SW14 address and mask defines
#pragma	ioport	CSA_1SW14_Data_ADDR:	0x0
BYTE			CSA_1SW14_Data_ADDR;
#pragma	ioport	CSA_1SW14_DriveMode_0_ADDR:	0x100
BYTE			CSA_1SW14_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW14_DriveMode_1_ADDR:	0x101
BYTE			CSA_1SW14_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW14_IntEn_ADDR:	0x1
BYTE			CSA_1SW14_IntEn_ADDR;
#define CSA_1SW14_MASK 0x80
#pragma	ioport	CSA_1SW14_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSA_1SW14_MUXBusCtrl_ADDR;
// CSA_1SW14 Shadow defines
//   CSA_1SW14_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define CSA_1SW14_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSA_1SW12 address and mask defines
#pragma	ioport	CSA_1SW12_Data_ADDR:	0x0
BYTE			CSA_1SW12_Data_ADDR;
#pragma	ioport	CSA_1SW12_DriveMode_0_ADDR:	0x100
BYTE			CSA_1SW12_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW12_DriveMode_1_ADDR:	0x101
BYTE			CSA_1SW12_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW12_IntEn_ADDR:	0x1
BYTE			CSA_1SW12_IntEn_ADDR;
#define CSA_1SW12_MASK 0x20
#pragma	ioport	CSA_1SW12_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSA_1SW12_MUXBusCtrl_ADDR;
// CSA_1SW12 Shadow defines
//   CSA_1SW12_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define CSA_1SW12_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// Port_0_3 address and mask defines
#pragma	ioport	Port_0_3_Data_ADDR:	0x0
BYTE			Port_0_3_Data_ADDR;
#pragma	ioport	Port_0_3_DriveMode_0_ADDR:	0x100
BYTE			Port_0_3_DriveMode_0_ADDR;
#pragma	ioport	Port_0_3_DriveMode_1_ADDR:	0x101
BYTE			Port_0_3_DriveMode_1_ADDR;
#pragma	ioport	Port_0_3_IntEn_ADDR:	0x1
BYTE			Port_0_3_IntEn_ADDR;
#define Port_0_3_MASK 0x8
#pragma	ioport	Port_0_3_MUXBusCtrl_ADDR:	0x1d8
BYTE			Port_0_3_MUXBusCtrl_ADDR;
// Port_0_3 Shadow defines
//   Port_0_3_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define Port_0_3_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)