psocgpioint.h

电容感应程序

/******************************************************************************
*  Generated by PSoC Designer ver 4.3  b1884 : 23 June, 2006
******************************************************************************/
#include <m8c.h>
/*
*   PSoCGPIOINT.h
*   Data: 04 June, 2002
*   Copyright Cypress MicroSystems 2002
*
*  This file is generated by the Device Editor on Application Generation.
*  It contains equates that are useful in writing code relating to GPIO
*  related values.
*  
*  DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
*  Edits to this file will not be preserved.
*/
// CSA_1SW8 address and mask defines
#pragma	ioport	CSA_1SW8_Data_ADDR:	0x0
BYTE			CSA_1SW8_Data_ADDR;
#pragma	ioport	CSA_1SW8_DriveMode_0_ADDR:	0x100
BYTE			CSA_1SW8_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW8_DriveMode_1_ADDR:	0x101
BYTE			CSA_1SW8_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW8_IntEn_ADDR:	0x1
BYTE			CSA_1SW8_IntEn_ADDR;
#define CSA_1SW8_MASK 0x2
#pragma	ioport	CSA_1SW8_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSA_1SW8_MUXBusCtrl_ADDR;
// CSA_1SW8 Shadow defines
//   CSA_1SW8_DataShadow define
extern unsigned char Port_0_Data_SHADE;
#define CSA_1SW8_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSA_1SW10 address and mask defines
#pragma	ioport	CSA_1SW10_Data_ADDR:	0x8
BYTE			CSA_1SW10_Data_ADDR;
#pragma	ioport	CSA_1SW10_DriveMode_0_ADDR:	0x108
BYTE			CSA_1SW10_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW10_DriveMode_1_ADDR:	0x109
BYTE			CSA_1SW10_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW10_IntEn_ADDR:	0x9
BYTE			CSA_1SW10_IntEn_ADDR;
#define CSA_1SW10_MASK 0x80
#pragma	ioport	CSA_1SW10_MUXBusCtrl_ADDR:	0x1da
BYTE			CSA_1SW10_MUXBusCtrl_ADDR;
// CSA_1SW10 Shadow defines
//   CSA_1SW10_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define CSA_1SW10_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   CSA_1SW10_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define CSA_1SW10_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   CSA_1SW10_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define CSA_1SW10_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// LCD_1RS address and mask defines
#pragma	ioport	LCD_1RS_Data_ADDR:	0x8
BYTE			LCD_1RS_Data_ADDR;
#pragma	ioport	LCD_1RS_DriveMode_0_ADDR:	0x108
BYTE			LCD_1RS_DriveMode_0_ADDR;
#pragma	ioport	LCD_1RS_DriveMode_1_ADDR:	0x109
BYTE			LCD_1RS_DriveMode_1_ADDR;
#pragma	ioport	LCD_1RS_IntEn_ADDR:	0x9
BYTE			LCD_1RS_IntEn_ADDR;
#define LCD_1RS_MASK 0x20
#pragma	ioport	LCD_1RS_MUXBusCtrl_ADDR:	0x1da
BYTE			LCD_1RS_MUXBusCtrl_ADDR;
// LCD_1RS Shadow defines
//   LCD_1RS_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define LCD_1RS_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   LCD_1RS_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define LCD_1RS_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   LCD_1RS_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define LCD_1RS_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// LCD_1D7 address and mask defines
#pragma	ioport	LCD_1D7_Data_ADDR:	0x8
BYTE			LCD_1D7_Data_ADDR;
#pragma	ioport	LCD_1D7_DriveMode_0_ADDR:	0x108
BYTE			LCD_1D7_DriveMode_0_ADDR;
#pragma	ioport	LCD_1D7_DriveMode_1_ADDR:	0x109
BYTE			LCD_1D7_DriveMode_1_ADDR;
#pragma	ioport	LCD_1D7_IntEn_ADDR:	0x9
BYTE			LCD_1D7_IntEn_ADDR;
#define LCD_1D7_MASK 0x8
#pragma	ioport	LCD_1D7_MUXBusCtrl_ADDR:	0x1da
BYTE			LCD_1D7_MUXBusCtrl_ADDR;
// LCD_1D7 Shadow defines
//   LCD_1D7_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define LCD_1D7_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   LCD_1D7_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define LCD_1D7_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   LCD_1D7_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define LCD_1D7_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// LCD_1D5 address and mask defines
#pragma	ioport	LCD_1D5_Data_ADDR:	0x8
BYTE			LCD_1D5_Data_ADDR;
#pragma	ioport	LCD_1D5_DriveMode_0_ADDR:	0x108
BYTE			LCD_1D5_DriveMode_0_ADDR;
#pragma	ioport	LCD_1D5_DriveMode_1_ADDR:	0x109
BYTE			LCD_1D5_DriveMode_1_ADDR;
#pragma	ioport	LCD_1D5_IntEn_ADDR:	0x9
BYTE			LCD_1D5_IntEn_ADDR;
#define LCD_1D5_MASK 0x2
#pragma	ioport	LCD_1D5_MUXBusCtrl_ADDR:	0x1da
BYTE			LCD_1D5_MUXBusCtrl_ADDR;
// LCD_1D5 Shadow defines
//   LCD_1D5_DataShadow define
extern unsigned char Port_2_Data_SHADE;
#define LCD_1D5_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
//   LCD_1D5_DriveMode_0Shadow define
extern unsigned char Port_2_DriveMode_0_SHADE;
#define LCD_1D5_DriveMode_0Shadow (*(unsigned char*)&Port_2_DriveMode_0_SHADE)
//   LCD_1D5_DriveMode_1Shadow define
extern unsigned char Port_2_DriveMode_1_SHADE;
#define LCD_1D5_DriveMode_1Shadow (*(unsigned char*)&Port_2_DriveMode_1_SHADE)
// CSA_1SW4 address and mask defines
#pragma	ioport	CSA_1SW4_Data_ADDR:	0xc
BYTE			CSA_1SW4_Data_ADDR;
#pragma	ioport	CSA_1SW4_DriveMode_0_ADDR:	0x10c
BYTE			CSA_1SW4_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW4_DriveMode_1_ADDR:	0x10d
BYTE			CSA_1SW4_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW4_IntEn_ADDR:	0xd
BYTE			CSA_1SW4_IntEn_ADDR;
#define CSA_1SW4_MASK 0x8
#pragma	ioport	CSA_1SW4_MUXBusCtrl_ADDR:	0x1db
BYTE			CSA_1SW4_MUXBusCtrl_ADDR;
// CSA_1SW4 Shadow defines
//   CSA_1SW4_DataShadow define
extern unsigned char Port_3_Data_SHADE;
#define CSA_1SW4_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// Port_3_1 address and mask defines
#pragma	ioport	Port_3_1_Data_ADDR:	0xc
BYTE			Port_3_1_Data_ADDR;
#pragma	ioport	Port_3_1_DriveMode_0_ADDR:	0x10c
BYTE			Port_3_1_DriveMode_0_ADDR;
#pragma	ioport	Port_3_1_DriveMode_1_ADDR:	0x10d
BYTE			Port_3_1_DriveMode_1_ADDR;
#pragma	ioport	Port_3_1_IntEn_ADDR:	0xd
BYTE			Port_3_1_IntEn_ADDR;
#define Port_3_1_MASK 0x2
#pragma	ioport	Port_3_1_MUXBusCtrl_ADDR:	0x1db
BYTE			Port_3_1_MUXBusCtrl_ADDR;
// Port_3_1 Shadow defines
//   Port_3_1_DataShadow define
extern unsigned char Port_3_Data_SHADE;
#define Port_3_1_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// Port_1_7 address and mask defines
#pragma	ioport	Port_1_7_Data_ADDR:	0x4
BYTE			Port_1_7_Data_ADDR;
#pragma	ioport	Port_1_7_DriveMode_0_ADDR:	0x104
BYTE			Port_1_7_DriveMode_0_ADDR;
#pragma	ioport	Port_1_7_DriveMode_1_ADDR:	0x105
BYTE			Port_1_7_DriveMode_1_ADDR;
#pragma	ioport	Port_1_7_IntEn_ADDR:	0x5
BYTE			Port_1_7_IntEn_ADDR;
#define Port_1_7_MASK 0x80
#pragma	ioport	Port_1_7_MUXBusCtrl_ADDR:	0x1d9
BYTE			Port_1_7_MUXBusCtrl_ADDR;
// Port_1_7 Shadow defines
//   Port_1_7_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define Port_1_7_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// Port_1_5 address and mask defines
#pragma	ioport	Port_1_5_Data_ADDR:	0x4
BYTE			Port_1_5_Data_ADDR;
#pragma	ioport	Port_1_5_DriveMode_0_ADDR:	0x104
BYTE			Port_1_5_DriveMode_0_ADDR;
#pragma	ioport	Port_1_5_DriveMode_1_ADDR:	0x105
BYTE			Port_1_5_DriveMode_1_ADDR;
#pragma	ioport	Port_1_5_IntEn_ADDR:	0x5
BYTE			Port_1_5_IntEn_ADDR;
#define Port_1_5_MASK 0x20
#pragma	ioport	Port_1_5_MUXBusCtrl_ADDR:	0x1d9
BYTE			Port_1_5_MUXBusCtrl_ADDR;
// Port_1_5 Shadow defines
//   Port_1_5_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define Port_1_5_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSA_1SW6 address and mask defines
#pragma	ioport	CSA_1SW6_Data_ADDR:	0x4
BYTE			CSA_1SW6_Data_ADDR;
#pragma	ioport	CSA_1SW6_DriveMode_0_ADDR:	0x104
BYTE			CSA_1SW6_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW6_DriveMode_1_ADDR:	0x105
BYTE			CSA_1SW6_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW6_IntEn_ADDR:	0x5
BYTE			CSA_1SW6_IntEn_ADDR;
#define CSA_1SW6_MASK 0x8
#pragma	ioport	CSA_1SW6_MUXBusCtrl_ADDR:	0x1d9
BYTE			CSA_1SW6_MUXBusCtrl_ADDR;
// CSA_1SW6 Shadow defines
//   CSA_1SW6_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define CSA_1SW6_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// Port_1_1 address and mask defines
#pragma	ioport	Port_1_1_Data_ADDR:	0x4
BYTE			Port_1_1_Data_ADDR;
#pragma	ioport	Port_1_1_DriveMode_0_ADDR:	0x104
BYTE			Port_1_1_DriveMode_0_ADDR;
#pragma	ioport	Port_1_1_DriveMode_1_ADDR:	0x105
BYTE			Port_1_1_DriveMode_1_ADDR;
#pragma	ioport	Port_1_1_IntEn_ADDR:	0x5
BYTE			Port_1_1_IntEn_ADDR;
#define Port_1_1_MASK 0x2
#pragma	ioport	Port_1_1_MUXBusCtrl_ADDR:	0x1d9
BYTE			Port_1_1_MUXBusCtrl_ADDR;
// Port_1_1 Shadow defines
//   Port_1_1_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define Port_1_1_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// Port_1_0 address and mask defines
#pragma	ioport	Port_1_0_Data_ADDR:	0x4
BYTE			Port_1_0_Data_ADDR;
#pragma	ioport	Port_1_0_DriveMode_0_ADDR:	0x104
BYTE			Port_1_0_DriveMode_0_ADDR;
#pragma	ioport	Port_1_0_DriveMode_1_ADDR:	0x105
BYTE			Port_1_0_DriveMode_1_ADDR;
#pragma	ioport	Port_1_0_IntEn_ADDR:	0x5
BYTE			Port_1_0_IntEn_ADDR;
#define Port_1_0_MASK 0x1
#pragma	ioport	Port_1_0_MUXBusCtrl_ADDR:	0x1d9
BYTE			Port_1_0_MUXBusCtrl_ADDR;
// Port_1_0 Shadow defines
//   Port_1_0_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define Port_1_0_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSA_1SW0 address and mask defines
#pragma	ioport	CSA_1SW0_Data_ADDR:	0x4
BYTE			CSA_1SW0_Data_ADDR;
#pragma	ioport	CSA_1SW0_DriveMode_0_ADDR:	0x104
BYTE			CSA_1SW0_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW0_DriveMode_1_ADDR:	0x105
BYTE			CSA_1SW0_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW0_IntEn_ADDR:	0x5
BYTE			CSA_1SW0_IntEn_ADDR;
#define CSA_1SW0_MASK 0x4
#pragma	ioport	CSA_1SW0_MUXBusCtrl_ADDR:	0x1d9
BYTE			CSA_1SW0_MUXBusCtrl_ADDR;
// CSA_1SW0 Shadow defines
//   CSA_1SW0_DataShadow define
extern unsigned char Port_1_Data_SHADE;
#define CSA_1SW0_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSA_1SW1 address and mask defines
#pragma	ioport	CSA_1SW1_Data_ADDR:	0x4
BYTE			CSA_1SW1_Data_ADDR;
#pragma	ioport	CSA_1SW1_DriveMode_0_ADDR:	0x104
BYTE			CSA_1SW1_DriveMode_0_ADDR;
#pragma	ioport	CSA_1SW1_DriveMode_1_ADDR:	0x105
BYTE			CSA_1SW1_DriveMode_1_ADDR;
#pragma	ioport	CSA_1SW1_IntEn_ADDR:	0x5
BYTE			CSA_1SW1_IntEn_ADDR;