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电容感应程序

endm
;   SetCSA_1SW1_Data macro
macro ClearCSA_1SW1_Data
	and		[Port_1_Data_SHADE], ~10h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSA_1SW2 address and mask equates
CSA_1SW2_Data_ADDR:	equ	4h
CSA_1SW2_DriveMode_0_ADDR:	equ	104h
CSA_1SW2_DriveMode_1_ADDR:	equ	105h
CSA_1SW2_IntEn_ADDR:	equ	5h
CSA_1SW2_MASK:	equ	40h
CSA_1SW2_MUXBusCtrl_ADDR:	equ	1d9h
; CSA_1SW2_Data access macros
;   GetCSA_1SW2_Data macro, return in a
macro GetCSA_1SW2_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 40h
endm
;   SetCSA_1SW2_Data macro
macro SetCSA_1SW2_Data
	or		[Port_1_Data_SHADE], 40h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSA_1SW2_Data macro
macro ClearCSA_1SW2_Data
	and		[Port_1_Data_SHADE], ~40h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSA_1SW5 address and mask equates
CSA_1SW5_Data_ADDR:	equ	ch
CSA_1SW5_DriveMode_0_ADDR:	equ	10ch
CSA_1SW5_DriveMode_1_ADDR:	equ	10dh
CSA_1SW5_IntEn_ADDR:	equ	dh
CSA_1SW5_MASK:	equ	1h
CSA_1SW5_MUXBusCtrl_ADDR:	equ	1dbh
; CSA_1SW5_Data access macros
;   GetCSA_1SW5_Data macro, return in a
macro GetCSA_1SW5_Data
	mov		a,[Port_3_Data_SHADE]
	and		a, 1h
endm
;   SetCSA_1SW5_Data macro
macro SetCSA_1SW5_Data
	or		[Port_3_Data_SHADE], 1h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm
;   SetCSA_1SW5_Data macro
macro ClearCSA_1SW5_Data
	and		[Port_3_Data_SHADE], ~1h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm

; CSA_1SW3 address and mask equates
CSA_1SW3_Data_ADDR:	equ	ch
CSA_1SW3_DriveMode_0_ADDR:	equ	10ch
CSA_1SW3_DriveMode_1_ADDR:	equ	10dh
CSA_1SW3_IntEn_ADDR:	equ	dh
CSA_1SW3_MASK:	equ	4h
CSA_1SW3_MUXBusCtrl_ADDR:	equ	1dbh
; CSA_1SW3_Data access macros
;   GetCSA_1SW3_Data macro, return in a
macro GetCSA_1SW3_Data
	mov		a,[Port_3_Data_SHADE]
	and		a, 4h
endm
;   SetCSA_1SW3_Data macro
macro SetCSA_1SW3_Data
	or		[Port_3_Data_SHADE], 4h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm
;   SetCSA_1SW3_Data macro
macro ClearCSA_1SW3_Data
	and		[Port_3_Data_SHADE], ~4h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm

; LCD_1D4 address and mask equates
LCD_1D4_Data_ADDR:	equ	8h
LCD_1D4_DriveMode_0_ADDR:	equ	108h
LCD_1D4_DriveMode_1_ADDR:	equ	109h
LCD_1D4_IntEn_ADDR:	equ	9h
LCD_1D4_MASK:	equ	1h
LCD_1D4_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1D4_Data access macros
;   GetLCD_1D4_Data macro, return in a
macro GetLCD_1D4_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 1h
endm
;   SetLCD_1D4_Data macro
macro SetLCD_1D4_Data
	or		[Port_2_Data_SHADE], 1h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1D4_Data macro
macro ClearLCD_1D4_Data
	and		[Port_2_Data_SHADE], ~1h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1D4_DriveMode_0 access macros
;   GetLCD_1D4_DriveMode_0 macro, return in a
macro GetLCD_1D4_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 1h
endm
;   SetLCD_1D4_DriveMode_0 macro
macro SetLCD_1D4_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 1h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1D4_DriveMode_0 macro
macro ClearLCD_1D4_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~1h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1D4_DriveMode_1 access macros
;   GetLCD_1D4_DriveMode_1 macro, return in a
macro GetLCD_1D4_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 1h
endm
;   SetLCD_1D4_DriveMode_1 macro
macro SetLCD_1D4_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 1h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1D4_DriveMode_1 macro
macro ClearLCD_1D4_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~1h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; LCD_1D6 address and mask equates
LCD_1D6_Data_ADDR:	equ	8h
LCD_1D6_DriveMode_0_ADDR:	equ	108h
LCD_1D6_DriveMode_1_ADDR:	equ	109h
LCD_1D6_IntEn_ADDR:	equ	9h
LCD_1D6_MASK:	equ	4h
LCD_1D6_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1D6_Data access macros
;   GetLCD_1D6_Data macro, return in a
macro GetLCD_1D6_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 4h
endm
;   SetLCD_1D6_Data macro
macro SetLCD_1D6_Data
	or		[Port_2_Data_SHADE], 4h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1D6_Data macro
macro ClearLCD_1D6_Data
	and		[Port_2_Data_SHADE], ~4h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1D6_DriveMode_0 access macros
;   GetLCD_1D6_DriveMode_0 macro, return in a
macro GetLCD_1D6_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 4h
endm
;   SetLCD_1D6_DriveMode_0 macro
macro SetLCD_1D6_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 4h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1D6_DriveMode_0 macro
macro ClearLCD_1D6_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~4h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1D6_DriveMode_1 access macros
;   GetLCD_1D6_DriveMode_1 macro, return in a
macro GetLCD_1D6_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 4h
endm
;   SetLCD_1D6_DriveMode_1 macro
macro SetLCD_1D6_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 4h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1D6_DriveMode_1 macro
macro ClearLCD_1D6_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~4h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; LCD_1E address and mask equates
LCD_1E_Data_ADDR:	equ	8h
LCD_1E_DriveMode_0_ADDR:	equ	108h
LCD_1E_DriveMode_1_ADDR:	equ	109h
LCD_1E_IntEn_ADDR:	equ	9h
LCD_1E_MASK:	equ	10h
LCD_1E_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1E_Data access macros
;   GetLCD_1E_Data macro, return in a
macro GetLCD_1E_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 10h
endm
;   SetLCD_1E_Data macro
macro SetLCD_1E_Data
	or		[Port_2_Data_SHADE], 10h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1E_Data macro
macro ClearLCD_1E_Data
	and		[Port_2_Data_SHADE], ~10h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1E_DriveMode_0 access macros
;   GetLCD_1E_DriveMode_0 macro, return in a
macro GetLCD_1E_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 10h
endm
;   SetLCD_1E_DriveMode_0 macro
macro SetLCD_1E_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 10h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1E_DriveMode_0 macro
macro ClearLCD_1E_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~10h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1E_DriveMode_1 access macros
;   GetLCD_1E_DriveMode_1 macro, return in a
macro GetLCD_1E_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 10h
endm
;   SetLCD_1E_DriveMode_1 macro
macro SetLCD_1E_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 10h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1E_DriveMode_1 macro
macro ClearLCD_1E_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~10h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; LCD_1RW address and mask equates
LCD_1RW_Data_ADDR:	equ	8h
LCD_1RW_DriveMode_0_ADDR:	equ	108h
LCD_1RW_DriveMode_1_ADDR:	equ	109h
LCD_1RW_IntEn_ADDR:	equ	9h
LCD_1RW_MASK:	equ	40h
LCD_1RW_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1RW_Data access macros
;   GetLCD_1RW_Data macro, return in a
macro GetLCD_1RW_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 40h
endm
;   SetLCD_1RW_Data macro
macro SetLCD_1RW_Data
	or		[Port_2_Data_SHADE], 40h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1RW_Data macro
macro ClearLCD_1RW_Data
	and		[Port_2_Data_SHADE], ~40h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1RW_DriveMode_0 access macros
;   GetLCD_1RW_DriveMode_0 macro, return in a
macro GetLCD_1RW_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 40h
endm
;   SetLCD_1RW_DriveMode_0 macro
macro SetLCD_1RW_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 40h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1RW_DriveMode_0 macro
macro ClearLCD_1RW_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~40h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1RW_DriveMode_1 access macros
;   GetLCD_1RW_DriveMode_1 macro, return in a
macro GetLCD_1RW_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 40h
endm
;   SetLCD_1RW_DriveMode_1 macro
macro SetLCD_1RW_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 40h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1RW_DriveMode_1 macro
macro ClearLCD_1RW_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~40h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; CSA_1SW7 address and mask equates
CSA_1SW7_Data_ADDR:	equ	0h
CSA_1SW7_DriveMode_0_ADDR:	equ	100h
CSA_1SW7_DriveMode_1_ADDR:	equ	101h
CSA_1SW7_IntEn_ADDR:	equ	1h
CSA_1SW7_MASK:	equ	1h
CSA_1SW7_MUXBusCtrl_ADDR:	equ	1d8h
; CSA_1SW7_Data access macros
;   GetCSA_1SW7_Data macro, return in a
macro GetCSA_1SW7_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 1h
endm
;   SetCSA_1SW7_Data macro
macro SetCSA_1SW7_Data
	or		[Port_0_Data_SHADE], 1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSA_1SW7_Data macro
macro ClearCSA_1SW7_Data
	and		[Port_0_Data_SHADE], ~1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSA_1SW9 address and mask equates
CSA_1SW9_Data_ADDR:	equ	0h
CSA_1SW9_DriveMode_0_ADDR:	equ	100h
CSA_1SW9_DriveMode_1_ADDR:	equ	101h
CSA_1SW9_IntEn_ADDR:	equ	1h
CSA_1SW9_MASK:	equ	4h
CSA_1SW9_MUXBusCtrl_ADDR:	equ	1d8h
; CSA_1SW9_Data access macros
;   GetCSA_1SW9_Data macro, return in a
macro GetCSA_1SW9_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 4h
endm
;   SetCSA_1SW9_Data macro
macro SetCSA_1SW9_Data
	or		[Port_0_Data_SHADE], 4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSA_1SW9_Data macro
macro ClearCSA_1SW9_Data
	and		[Port_0_Data_SHADE], ~4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSA_1SW11 address and mask equates
CSA_1SW11_Data_ADDR:	equ	0h
CSA_1SW11_DriveMode_0_ADDR:	equ	100h
CSA_1SW11_DriveMode_1_ADDR:	equ	101h
CSA_1SW11_IntEn_ADDR:	equ	1h
CSA_1SW11_MASK:	equ	10h
CSA_1SW11_MUXBusCtrl_ADDR:	equ	1d8h
; CSA_1SW11_Data access macros
;   GetCSA_1SW11_Data macro, return in a
macro GetCSA_1SW11_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 10h
endm
;   SetCSA_1SW11_Data macro
macro SetCSA_1SW11_Data
	or		[Port_0_Data_SHADE], 10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSA_1SW11_Data macro
macro ClearCSA_1SW11_Data
	and		[Port_0_Data_SHADE], ~10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSA_1SW13 address and mask equates
CSA_1SW13_Data_ADDR:	equ	0h
CSA_1SW13_DriveMode_0_ADDR:	equ	100h
CSA_1SW13_DriveMode_1_ADDR:	equ	101h
CSA_1SW13_IntEn_ADDR:	equ	1h
CSA_1SW13_MASK:	equ	40h
CSA_1SW13_MUXBusCtrl_ADDR:	equ	1d8h
; CSA_1SW13_Data access macros
;   GetCSA_1SW13_Data macro, return in a
macro GetCSA_1SW13_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 40h
endm
;   SetCSA_1SW13_Data macro
macro SetCSA_1SW13_Data
	or		[Port_0_Data_SHADE], 40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSA_1SW13_Data macro
macro ClearCSA_1SW13_Data
	and		[Port_0_Data_SHADE], ~40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSA_1SW14 address and mask equates
CSA_1SW14_Data_ADDR:	equ	0h
CSA_1SW14_DriveMode_0_ADDR:	equ	100h
CSA_1SW14_DriveMode_1_ADDR:	equ	101h
CSA_1SW14_IntEn_ADDR:	equ	1h
CSA_1SW14_MASK:	equ	80h
CSA_1SW14_MUXBusCtrl_ADDR:	equ	1d8h
; CSA_1SW14_Data access macros
;   GetCSA_1SW14_Data macro, return in a
macro GetCSA_1SW14_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 80h
endm
;   SetCSA_1SW14_Data macro
macro SetCSA_1SW14_Data
	or		[Port_0_Data_SHADE], 80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSA_1SW14_Data macro
macro ClearCSA_1SW14_Data
	and		[Port_0_Data_SHADE], ~80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSA_1SW12 address and mask equates
CSA_1SW12_Data_ADDR:	equ	0h
CSA_1SW12_DriveMode_0_ADDR:	equ	100h
CSA_1SW12_DriveMode_1_ADDR:	equ	101h
CSA_1SW12_IntEn_ADDR:	equ	1h
CSA_1SW12_MASK:	equ	20h
CSA_1SW12_MUXBusCtrl_ADDR:	equ	1d8h
; CSA_1SW12_Data access macros
;   GetCSA_1SW12_Data macro, return in a
macro GetCSA_1SW12_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 20h
endm
;   SetCSA_1SW12_Data macro
macro SetCSA_1SW12_Data
	or		[Port_0_Data_SHADE], 20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSA_1SW12_Data macro
macro ClearCSA_1SW12_Data
	and		[Port_0_Data_SHADE], ~20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; Port_0_3 address and mask equates
Port_0_3_Data_ADDR:	equ	0h
Port_0_3_DriveMode_0_ADDR:	equ	100h
Port_0_3_DriveMode_1_ADDR:	equ	101h
Port_0_3_IntEn_ADDR:	equ	1h
Port_0_3_MASK:	equ	8h
Port_0_3_MUXBusCtrl_ADDR:	equ	1d8h
; Port_0_3_Data access macros
;   GetPort_0_3_Data macro, return in a
macro GetPort_0_3_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 8h
endm
;   SetPort_0_3_Data macro
macro SetPort_0_3_Data
	or		[Port_0_Data_SHADE], 8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetPort_0_3_Data macro
macro ClearPort_0_3_Data
	and		[Port_0_Data_SHADE], ~8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm