psocgpioint.inc

电容感应程序

; Generated by PSoC Designer ver 4.3  b1884 : 23 June, 2006
;
;
;  PSoCGPIOINT.inc
;
;  Data: 29 October, 2001
;  Copyright Cypress MicroSystems 2001
;
;  This file is generated by the Device Editor on Application Generation.
;  It contains equates that are useful in writing code relating to GPIO
;  related interrupts.
;  
;  DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
;  Edits to this file will not be preserved.
;
; CSA_1SW8 address and mask equates
CSA_1SW8_Data_ADDR:	equ	0h
CSA_1SW8_DriveMode_0_ADDR:	equ	100h
CSA_1SW8_DriveMode_1_ADDR:	equ	101h
CSA_1SW8_IntEn_ADDR:	equ	1h
CSA_1SW8_MASK:	equ	2h
CSA_1SW8_MUXBusCtrl_ADDR:	equ	1d8h
; CSA_1SW8_Data access macros
;   GetCSA_1SW8_Data macro, return in a
macro GetCSA_1SW8_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 2h
endm
;   SetCSA_1SW8_Data macro
macro SetCSA_1SW8_Data
	or		[Port_0_Data_SHADE], 2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSA_1SW8_Data macro
macro ClearCSA_1SW8_Data
	and		[Port_0_Data_SHADE], ~2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSA_1SW10 address and mask equates
CSA_1SW10_Data_ADDR:	equ	8h
CSA_1SW10_DriveMode_0_ADDR:	equ	108h
CSA_1SW10_DriveMode_1_ADDR:	equ	109h
CSA_1SW10_IntEn_ADDR:	equ	9h
CSA_1SW10_MASK:	equ	80h
CSA_1SW10_MUXBusCtrl_ADDR:	equ	1dah
; CSA_1SW10_Data access macros
;   GetCSA_1SW10_Data macro, return in a
macro GetCSA_1SW10_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 80h
endm
;   SetCSA_1SW10_Data macro
macro SetCSA_1SW10_Data
	or		[Port_2_Data_SHADE], 80h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetCSA_1SW10_Data macro
macro ClearCSA_1SW10_Data
	and		[Port_2_Data_SHADE], ~80h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; CSA_1SW10_DriveMode_0 access macros
;   GetCSA_1SW10_DriveMode_0 macro, return in a
macro GetCSA_1SW10_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 80h
endm
;   SetCSA_1SW10_DriveMode_0 macro
macro SetCSA_1SW10_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 80h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetCSA_1SW10_DriveMode_0 macro
macro ClearCSA_1SW10_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~80h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; CSA_1SW10_DriveMode_1 access macros
;   GetCSA_1SW10_DriveMode_1 macro, return in a
macro GetCSA_1SW10_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 80h
endm
;   SetCSA_1SW10_DriveMode_1 macro
macro SetCSA_1SW10_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 80h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetCSA_1SW10_DriveMode_1 macro
macro ClearCSA_1SW10_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~80h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; LCD_1RS address and mask equates
LCD_1RS_Data_ADDR:	equ	8h
LCD_1RS_DriveMode_0_ADDR:	equ	108h
LCD_1RS_DriveMode_1_ADDR:	equ	109h
LCD_1RS_IntEn_ADDR:	equ	9h
LCD_1RS_MASK:	equ	20h
LCD_1RS_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1RS_Data access macros
;   GetLCD_1RS_Data macro, return in a
macro GetLCD_1RS_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 20h
endm
;   SetLCD_1RS_Data macro
macro SetLCD_1RS_Data
	or		[Port_2_Data_SHADE], 20h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1RS_Data macro
macro ClearLCD_1RS_Data
	and		[Port_2_Data_SHADE], ~20h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1RS_DriveMode_0 access macros
;   GetLCD_1RS_DriveMode_0 macro, return in a
macro GetLCD_1RS_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 20h
endm
;   SetLCD_1RS_DriveMode_0 macro
macro SetLCD_1RS_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 20h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1RS_DriveMode_0 macro
macro ClearLCD_1RS_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~20h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1RS_DriveMode_1 access macros
;   GetLCD_1RS_DriveMode_1 macro, return in a
macro GetLCD_1RS_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 20h
endm
;   SetLCD_1RS_DriveMode_1 macro
macro SetLCD_1RS_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 20h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1RS_DriveMode_1 macro
macro ClearLCD_1RS_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~20h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; LCD_1D7 address and mask equates
LCD_1D7_Data_ADDR:	equ	8h
LCD_1D7_DriveMode_0_ADDR:	equ	108h
LCD_1D7_DriveMode_1_ADDR:	equ	109h
LCD_1D7_IntEn_ADDR:	equ	9h
LCD_1D7_MASK:	equ	8h
LCD_1D7_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1D7_Data access macros
;   GetLCD_1D7_Data macro, return in a
macro GetLCD_1D7_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 8h
endm
;   SetLCD_1D7_Data macro
macro SetLCD_1D7_Data
	or		[Port_2_Data_SHADE], 8h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1D7_Data macro
macro ClearLCD_1D7_Data
	and		[Port_2_Data_SHADE], ~8h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1D7_DriveMode_0 access macros
;   GetLCD_1D7_DriveMode_0 macro, return in a
macro GetLCD_1D7_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 8h
endm
;   SetLCD_1D7_DriveMode_0 macro
macro SetLCD_1D7_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 8h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1D7_DriveMode_0 macro
macro ClearLCD_1D7_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~8h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1D7_DriveMode_1 access macros
;   GetLCD_1D7_DriveMode_1 macro, return in a
macro GetLCD_1D7_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 8h
endm
;   SetLCD_1D7_DriveMode_1 macro
macro SetLCD_1D7_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 8h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1D7_DriveMode_1 macro
macro ClearLCD_1D7_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~8h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; LCD_1D5 address and mask equates
LCD_1D5_Data_ADDR:	equ	8h
LCD_1D5_DriveMode_0_ADDR:	equ	108h
LCD_1D5_DriveMode_1_ADDR:	equ	109h
LCD_1D5_IntEn_ADDR:	equ	9h
LCD_1D5_MASK:	equ	2h
LCD_1D5_MUXBusCtrl_ADDR:	equ	1dah
; LCD_1D5_Data access macros
;   GetLCD_1D5_Data macro, return in a
macro GetLCD_1D5_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 2h
endm
;   SetLCD_1D5_Data macro
macro SetLCD_1D5_Data
	or		[Port_2_Data_SHADE], 2h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetLCD_1D5_Data macro
macro ClearLCD_1D5_Data
	and		[Port_2_Data_SHADE], ~2h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; LCD_1D5_DriveMode_0 access macros
;   GetLCD_1D5_DriveMode_0 macro, return in a
macro GetLCD_1D5_DriveMode_0
	mov		a,[Port_2_DriveMode_0_SHADE]
	and		a, 2h
endm
;   SetLCD_1D5_DriveMode_0 macro
macro SetLCD_1D5_DriveMode_0
	or		[Port_2_DriveMode_0_SHADE], 2h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm
;   SetLCD_1D5_DriveMode_0 macro
macro ClearLCD_1D5_DriveMode_0
	and		[Port_2_DriveMode_0_SHADE], ~2h
	mov		reg[Port_2_DriveMode_0], [Port_2_DriveMode_0_SHADE]
endm

; LCD_1D5_DriveMode_1 access macros
;   GetLCD_1D5_DriveMode_1 macro, return in a
macro GetLCD_1D5_DriveMode_1
	mov		a,[Port_2_DriveMode_1_SHADE]
	and		a, 2h
endm
;   SetLCD_1D5_DriveMode_1 macro
macro SetLCD_1D5_DriveMode_1
	or		[Port_2_DriveMode_1_SHADE], 2h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm
;   SetLCD_1D5_DriveMode_1 macro
macro ClearLCD_1D5_DriveMode_1
	and		[Port_2_DriveMode_1_SHADE], ~2h
	mov		reg[Port_2_DriveMode_1], [Port_2_DriveMode_1_SHADE]
endm

; CSA_1SW4 address and mask equates
CSA_1SW4_Data_ADDR:	equ	ch
CSA_1SW4_DriveMode_0_ADDR:	equ	10ch
CSA_1SW4_DriveMode_1_ADDR:	equ	10dh
CSA_1SW4_IntEn_ADDR:	equ	dh
CSA_1SW4_MASK:	equ	8h
CSA_1SW4_MUXBusCtrl_ADDR:	equ	1dbh
; CSA_1SW4_Data access macros
;   GetCSA_1SW4_Data macro, return in a
macro GetCSA_1SW4_Data
	mov		a,[Port_3_Data_SHADE]
	and		a, 8h
endm
;   SetCSA_1SW4_Data macro
macro SetCSA_1SW4_Data
	or		[Port_3_Data_SHADE], 8h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm
;   SetCSA_1SW4_Data macro
macro ClearCSA_1SW4_Data
	and		[Port_3_Data_SHADE], ~8h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm

; Port_3_1 address and mask equates
Port_3_1_Data_ADDR:	equ	ch
Port_3_1_DriveMode_0_ADDR:	equ	10ch
Port_3_1_DriveMode_1_ADDR:	equ	10dh
Port_3_1_IntEn_ADDR:	equ	dh
Port_3_1_MASK:	equ	2h
Port_3_1_MUXBusCtrl_ADDR:	equ	1dbh
; Port_3_1_Data access macros
;   GetPort_3_1_Data macro, return in a
macro GetPort_3_1_Data
	mov		a,[Port_3_Data_SHADE]
	and		a, 2h
endm
;   SetPort_3_1_Data macro
macro SetPort_3_1_Data
	or		[Port_3_Data_SHADE], 2h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm
;   SetPort_3_1_Data macro
macro ClearPort_3_1_Data
	and		[Port_3_Data_SHADE], ~2h
	mov		reg[Port_3_Data], [Port_3_Data_SHADE]
endm

; Port_1_7 address and mask equates
Port_1_7_Data_ADDR:	equ	4h
Port_1_7_DriveMode_0_ADDR:	equ	104h
Port_1_7_DriveMode_1_ADDR:	equ	105h
Port_1_7_IntEn_ADDR:	equ	5h
Port_1_7_MASK:	equ	80h
Port_1_7_MUXBusCtrl_ADDR:	equ	1d9h
; Port_1_7_Data access macros
;   GetPort_1_7_Data macro, return in a
macro GetPort_1_7_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 80h
endm
;   SetPort_1_7_Data macro
macro SetPort_1_7_Data
	or		[Port_1_Data_SHADE], 80h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetPort_1_7_Data macro
macro ClearPort_1_7_Data
	and		[Port_1_Data_SHADE], ~80h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; Port_1_5 address and mask equates
Port_1_5_Data_ADDR:	equ	4h
Port_1_5_DriveMode_0_ADDR:	equ	104h
Port_1_5_DriveMode_1_ADDR:	equ	105h
Port_1_5_IntEn_ADDR:	equ	5h
Port_1_5_MASK:	equ	20h
Port_1_5_MUXBusCtrl_ADDR:	equ	1d9h
; Port_1_5_Data access macros
;   GetPort_1_5_Data macro, return in a
macro GetPort_1_5_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 20h
endm
;   SetPort_1_5_Data macro
macro SetPort_1_5_Data
	or		[Port_1_Data_SHADE], 20h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetPort_1_5_Data macro
macro ClearPort_1_5_Data
	and		[Port_1_Data_SHADE], ~20h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSA_1SW6 address and mask equates
CSA_1SW6_Data_ADDR:	equ	4h
CSA_1SW6_DriveMode_0_ADDR:	equ	104h
CSA_1SW6_DriveMode_1_ADDR:	equ	105h
CSA_1SW6_IntEn_ADDR:	equ	5h
CSA_1SW6_MASK:	equ	8h
CSA_1SW6_MUXBusCtrl_ADDR:	equ	1d9h
; CSA_1SW6_Data access macros
;   GetCSA_1SW6_Data macro, return in a
macro GetCSA_1SW6_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 8h
endm
;   SetCSA_1SW6_Data macro
macro SetCSA_1SW6_Data
	or		[Port_1_Data_SHADE], 8h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSA_1SW6_Data macro
macro ClearCSA_1SW6_Data
	and		[Port_1_Data_SHADE], ~8h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; Port_1_1 address and mask equates
Port_1_1_Data_ADDR:	equ	4h
Port_1_1_DriveMode_0_ADDR:	equ	104h
Port_1_1_DriveMode_1_ADDR:	equ	105h
Port_1_1_IntEn_ADDR:	equ	5h
Port_1_1_MASK:	equ	2h
Port_1_1_MUXBusCtrl_ADDR:	equ	1d9h
; Port_1_1_Data access macros
;   GetPort_1_1_Data macro, return in a
macro GetPort_1_1_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 2h
endm
;   SetPort_1_1_Data macro
macro SetPort_1_1_Data
	or		[Port_1_Data_SHADE], 2h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetPort_1_1_Data macro
macro ClearPort_1_1_Data
	and		[Port_1_Data_SHADE], ~2h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; Port_1_0 address and mask equates
Port_1_0_Data_ADDR:	equ	4h
Port_1_0_DriveMode_0_ADDR:	equ	104h
Port_1_0_DriveMode_1_ADDR:	equ	105h
Port_1_0_IntEn_ADDR:	equ	5h
Port_1_0_MASK:	equ	1h
Port_1_0_MUXBusCtrl_ADDR:	equ	1d9h
; Port_1_0_Data access macros
;   GetPort_1_0_Data macro, return in a
macro GetPort_1_0_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 1h
endm
;   SetPort_1_0_Data macro
macro SetPort_1_0_Data
	or		[Port_1_Data_SHADE], 1h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetPort_1_0_Data macro
macro ClearPort_1_0_Data
	and		[Port_1_Data_SHADE], ~1h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSA_1SW0 address and mask equates
CSA_1SW0_Data_ADDR:	equ	4h
CSA_1SW0_DriveMode_0_ADDR:	equ	104h
CSA_1SW0_DriveMode_1_ADDR:	equ	105h
CSA_1SW0_IntEn_ADDR:	equ	5h
CSA_1SW0_MASK:	equ	4h
CSA_1SW0_MUXBusCtrl_ADDR:	equ	1d9h
; CSA_1SW0_Data access macros
;   GetCSA_1SW0_Data macro, return in a
macro GetCSA_1SW0_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 4h
endm
;   SetCSA_1SW0_Data macro
macro SetCSA_1SW0_Data
	or		[Port_1_Data_SHADE], 4h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSA_1SW0_Data macro
macro ClearCSA_1SW0_Data
	and		[Port_1_Data_SHADE], ~4h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSA_1SW1 address and mask equates
CSA_1SW1_Data_ADDR:	equ	4h
CSA_1SW1_DriveMode_0_ADDR:	equ	104h
CSA_1SW1_DriveMode_1_ADDR:	equ	105h
CSA_1SW1_IntEn_ADDR:	equ	5h
CSA_1SW1_MASK:	equ	10h
CSA_1SW1_MUXBusCtrl_ADDR:	equ	1d9h
; CSA_1SW1_Data access macros
;   GetCSA_1SW1_Data macro, return in a
macro GetCSA_1SW1_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 10h
endm
;   SetCSA_1SW1_Data macro
macro SetCSA_1SW1_Data
	or		[Port_1_Data_SHADE], 10h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]