📄 adc.lst
字号:
(0456)
(0457) ; Global Interrupt are NOT enabled, this should be done in main().
(0458) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0459) ; Global Interrupts should be enabled as soon as possible in main().
(0460) ;
011A: 62 E2 00 MOV REG[226],0 (0461) mov reg[INT_VC],0 ; Clear any pending interrupts which may
(0462) ; have been set during the boot process.
(0463) IF ENABLE_LJMP_TO_MAIN
(0464) ljmp _main ; goto main (no return)
(0465) ELSE
011D: 7C 04 B5 LCALL _main (0466) lcall _main ; call main
(0467) .Exit:
0120: 8F FF JMP 0x0120 (0468) jmp .Exit ; Wait here after return till power-off or reset
(0469) ENDIF
(0470)
(0471) ;---------------------------------
(0472) ; Library Access to Global Parms
(0473) ;---------------------------------
(0474) ;
(0475) bGetPowerSetting:
(0476) _bGetPowerSetting:
(0477) ; Returns value of POWER_SETTING in the A register.
(0478) ; No inputs. No Side Effects.
(0479) ;
(0480) IF (POWER_SETTING & POWER_SET_2V7)
(0481) mov A, POWER_SETTING | POWER_SET_SLOW_IMO
(0482) ELSE
0122: 50 10 MOV A,16 (0483) mov A, POWER_SETTING ; Supply voltage and internal main osc
(0484) ENDIF
0124: 7F RET (0485) ret
0125: 30 HALT
0126: 30 HALT
0127: 30 HALT
0128: 30 HALT
0129: 30 HALT
012A: 30 HALT
012B: 30 HALT
012C: 30 HALT
012D: 30 HALT
012E: 30 HALT
012F: 30 HALT
0130: 30 HALT
0131: 30 HALT
0132: 30 HALT
0133: 30 HALT
0134: 30 HALT
0135: 30 HALT
0136: 30 HALT
0137: 30 HALT
0138: 30 HALT
0139: 30 HALT
013A: 30 HALT
013B: 30 HALT
013C: 30 HALT
013D: 30 HALT
013E: 30 HALT
013F: 30 HALT
0140: 30 HALT
0141: 30 HALT
0142: 30 HALT
0143: 30 HALT
0144: 30 HALT
0145: 30 HALT
0146: 30 HALT
0147: 30 HALT
0148: 30 HALT
0149: 30 HALT
014A: 30 HALT
014B: 30 HALT
014C: 30 HALT
014D: 30 HALT
014E: 30 HALT
014F: 30 HALT
0150: 05 16 ADD [X+22],A
FILE: lib\psocconfigtbl.asm
(0001) ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
(0002) ;
(0003) include "m8c.inc"
(0004) ; Personalization tables
(0005) export LoadConfigTBL_adc
(0006) AREA psoc_config(rom, rel)
(0007) LoadConfigTBL_adc:
(0008) ; Ordered Global Register values
0152: 71 10 OR F,16 (0009) M8C_SetBank1
0154: 62 00 20 MOV REG[0],32 (0010) mov reg[00h], 20h ; Port_0_DriveMode_0 register (PRT0DM0)
0157: 62 01 DF MOV REG[1],223 (0011) mov reg[01h], dfh ; Port_0_DriveMode_1 register (PRT0DM1)
015A: 70 EF AND F,239 (0012) M8C_SetBank0
015C: 62 03 DF MOV REG[3],223 (0013) mov reg[03h], dfh ; Port_0_DriveMode_2 register (PRT0DM2)
015F: 62 02 20 MOV REG[2],32 (0014) mov reg[02h], 20h ; Port_0_GlobalSelect register (PRT0GS)
0162: 71 10 OR F,16 (0015) M8C_SetBank1
0164: 62 02 00 MOV REG[2],0 (0016) mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
0167: 62 03 00 MOV REG[3],0 (0017) mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
016A: 70 EF AND F,239 (0018) M8C_SetBank0
016C: 62 01 00 MOV REG[1],0 (0019) mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
016F: 71 10 OR F,16 (0020) M8C_SetBank1
0171: 62 04 00 MOV REG[4],0 (0021) mov reg[04h], 00h ; Port_1_DriveMode_0 register (PRT1DM0)
0174: 62 05 FF MOV REG[5],255 (0022) mov reg[05h], ffh ; Port_1_DriveMode_1 register (PRT1DM1)
0177: 70 EF AND F,239 (0023) M8C_SetBank0
0179: 62 07 FF MOV REG[7],255 (0024) mov reg[07h], ffh ; Port_1_DriveMode_2 register (PRT1DM2)
017C: 62 06 00 MOV REG[6],0 (0025) mov reg[06h], 00h ; Port_1_GlobalSelect register (PRT1GS)
017F: 71 10 OR F,16 (0026) M8C_SetBank1
0181: 62 06 00 MOV REG[6],0 (0027) mov reg[06h], 00h ; Port_1_IntCtrl_0 register (PRT1IC0)
0184: 62 07 00 MOV REG[7],0 (0028) mov reg[07h], 00h ; Port_1_IntCtrl_1 register (PRT1IC1)
0187: 70 EF AND F,239 (0029) M8C_SetBank0
0189: 62 05 00 MOV REG[5],0 (0030) mov reg[05h], 00h ; Port_1_IntEn register (PRT1IE)
018C: 71 10 OR F,16 (0031) M8C_SetBank1
018E: 62 08 00 MOV REG[8],0 (0032) mov reg[08h], 00h ; Port_2_DriveMode_0 register (PRT2DM0)
0191: 62 09 FF MOV REG[9],255 (0033) mov reg[09h], ffh ; Port_2_DriveMode_1 register (PRT2DM1)
0194: 70 EF AND F,239 (0034) M8C_SetBank0
0196: 62 0B FF MOV REG[11],255 (0035) mov reg[0bh], ffh ; Port_2_DriveMode_2 register (PRT2DM2)
0199: 62 0A 00 MOV REG[10],0 (0036) mov reg[0ah], 00h ; Port_2_GlobalSelect register (PRT2GS)
019C: 71 10 OR F,16 (0037) M8C_SetBank1
019E: 62 0A 00 MOV REG[10],0 (0038) mov reg[0ah], 00h ; Port_2_IntCtrl_0 register (PRT2IC0)
01A1: 62 0B 00 MOV REG[11],0 (0039) mov reg[0bh], 00h ; Port_2_IntCtrl_1 register (PRT2IC1)
01A4: 70 EF AND F,239 (0040) M8C_SetBank0
01A6: 62 09 00 MOV REG[9],0 (0041) mov reg[09h], 00h ; Port_2_IntEn register (PRT2IE)
01A9: 71 10 OR F,16 (0042) M8C_SetBank1
01AB: 62 0C 00 MOV REG[12],0 (0043) mov reg[0ch], 00h ; Port_3_DriveMode_0 register (PRT3DM0)
01AE: 62 0D 0F MOV REG[13],15 (0044) mov reg[0dh], 0fh ; Port_3_DriveMode_1 register (PRT3DM1)
01B1: 70 EF AND F,239 (0045) M8C_SetBank0
01B3: 62 0F 0F MOV REG[15],15 (0046) mov reg[0fh], 0fh ; Port_3_DriveMode_2 register (PRT3DM2)
01B6: 62 0E 00 MOV REG[14],0 (0047) mov reg[0eh], 00h ; Port_3_GlobalSelect register (PRT3GS)
01B9: 71 10 OR F,16 (0048) M8C_SetBank1
01BB: 62 0E 00 MOV REG[14],0 (0049) mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
01BE: 62 0F 00 MOV REG[15],0 (0050) mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
01C1: 70 EF AND F,239 (0051) M8C_SetBank0
01C3: 62 0D 00 MOV REG[13],0 (0052) mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
01C6: 70 EF AND F,239 (0053) M8C_SetBank0
(0054) ; Global Register values
01C8: 62 60 0B MOV REG[96],11 (0055) mov reg[60h], 0bh ; AnalogColumnInputSelect register (AMX_IN)
01CB: 62 64 00 MOV REG[100],0 (0056) mov reg[64h], 00h ; AnalogComparatorControl0 register (CMP_CR0)
01CE: 62 66 00 MOV REG[102],0 (0057) mov reg[66h], 00h ; AnalogComparatorControl1 register (CMP_CR1)
01D1: 62 61 00 MOV REG[97],0 (0058) mov reg[61h], 00h ; AnalogMuxBusConfig register (AMUXCFG)
01D4: 62 FD 00 MOV REG[253],0 (0059) mov reg[fdh], 00h ; DAC_Data register (DAC_D)
01D7: 62 E6 10 MOV REG[230],16 (0060) mov reg[e6h], 10h ; DecimatorControl_0 register (DEC_CR0)
01DA: 62 E7 00 MOV REG[231],0 (0061) mov reg[e7h], 00h ; DecimatorControl_1 register (DEC_CR1)
01DD: 62 D6 00 MOV REG[214],0 (0062) mov reg[d6h], 00h ; I2CConfig register (I2CCFG)
01E0: 62 62 00 MOV REG[98],0 (0063) mov reg[62h], 00h ; PWM_Control register (PWM_CR)
01E3: 62 B0 00 MOV REG[176],0 (0064) mov reg[b0h], 00h ; Row_0_InputMux register (RDI0RI)
01E6: 62 B1 00 MOV REG[177],0 (0065) mov reg[b1h], 00h ; Row_0_InputSync register (RDI0SYN)
01E9: 62 B2 00 MOV REG[178],0 (0066) mov reg[b2h], 00h ; Row_0_LogicInputAMux register (RDI0IS)
01EC: 62 B3 33 MOV REG[179],51 (0067) mov reg[b3h], 33h ; Row_0_LogicSelect_0 register (RDI0LT0)
01EF: 62 B4 33 MOV REG[180],51 (0068) mov reg[b4h], 33h ; Row_0_LogicSelect_1 register (RDI0LT1)
01F2: 62 B5 20 MOV REG[181],32 (0069) mov reg[b5h], 20h ; Row_0_OutputDrive_0 register (RDI0SRO0)
01F5: 62 B6 00 MOV REG[182],0 (0070) mov reg[b6h], 00h ; Row_0_OutputDrive_1 register (RDI0SRO1)
(0071) ; Instance name ADC10_1, User Module ADC10
(0072) ; Instance name ADC10_1, Block Name ADC(ACE00)
01F8: 62 72 69 MOV REG[114],105 (0073) mov reg[72h], 69h ;ADC10_1_ACE_CR1(ACE00CR1)
01FB: 62 73 00 MOV REG[115],0 (0074) mov reg[73h], 00h ;ADC10_1_ACE_CR2(ACE00CR2)
(0075) ; Instance name ADC10_1, Block Name CNT(DBB00)
01FE: 62 23 00 MOV REG[35],0 (0076) mov reg[23h], 00h ;ADC10_1_CNT_CR0(DBB00CR0)
0201: 62 21 00 MOV REG[33],0 (0077) mov reg[21h], 00h ;ADC10_1_CNT_DR1(DBB00DR1)
0204: 62 22 00 MOV REG[34],0 (0078) mov reg[22h], 00h ;ADC10_1_CNT_DR2(DBB00DR2)
(0079) ; Instance name ADC10_1, Block Name RAMP(ASE10)
0207: 62 68 24 MOV REG[104],36 (0080) mov reg[68h], 24h ;ADC10_1_ADC_CR(ADC0_CR)
020A: 62 80 00 MOV REG[128],0 (0081) mov reg[80h], 00h ;ADC10_1_ASE_CR0(ASE10CR0)
(0082) ; Instance name TX8_1, User Module TX8
(0083) ; Instance name TX8_1, Block Name TX8(DCB02)
020D: 62 2B 00 MOV REG[43],0 (0084) mov reg[2bh], 00h ;TX8_1_CONTROL_REG (DCB02CR0)
0210: 62 29 00 MOV REG[41],0 (0085) mov reg[29h], 00h ;TX8_1_TX_BUFFER_REG(DCB02DR1)
0213: 62 2A 00 MOV REG[42],0 (0086) mov reg[2ah], 00h ;TX8_1_(DCB02DR2)
0216: 71 10 OR F,16 (0087) M8C_SetBank1
(0088) ; Global Register values
0218: 62 61 00 MOV REG[97],0 (0089) mov reg[61h], 00h ; AnalogClockSelect1 register (CLK_CR1)
021B: 62 60 00 MOV REG[96],0 (0090) mov reg[60h], 00h ; AnalogColumnClockSelect register (CLK_CR0)
021E: 62 62 00 MOV REG[98],0 (0091) mov reg[62h], 00h ; AnalogIOControl_0 register (ABF_CR0)
0221: 62 67 33 MOV REG[103],51 (0092) mov reg[67h], 33h ; AnalogLUTControl0 register (ALT_CR0)
0224: 62 64 00 MOV REG[100],0 (0093) mov reg[64h], 00h ; ComparatorGlobalOutEn register (CMP_GO_EN)
0227: 62 FD 00 MOV REG[253],0 (0094) mov reg[fdh], 00h ; DAC_Control register (DAC_CR)
022A: 62 D1 00 MOV REG[209],0 (0095) mov reg[d1h], 00h ; GlobalDigitalInterconnect_Drive_Even_Input register (GDI_E_IN)
022D: 62 D3 00 MOV REG[211],0 (0096) mov reg[d3h], 00h ; GlobalDigitalInterconnect_Drive_Even_Output register (GDI_E_OU)
0230: 62 D0 00 MOV REG[208],0 (0097) mov reg[d0h], 00h ; GlobalDigitalInterconnect_Drive_Odd_Input register (GDI_O_IN)
0233: 62 D2 00 MOV REG[210],0 (0098) mov reg[d2h], 00h ; GlobalDigitalInterconnect_Drive_Odd_Output register (GDI_O_OU)
0236: 62 E1 00 MOV REG[225],0 (0099) mov reg[e1h], 00h ; OscillatorControl_1 register (OSC_CR1)
0239: 62 E2 00 MOV REG[226],0 (0100) mov reg[e2h], 00h ; OscillatorControl_2 register (OSC_CR2)
023C: 62 DF 00 MOV REG[223],0 (0101) mov reg[dfh], 00h ; OscillatorControl_3 register (OSC_CR3)
023F: 62 DE 00 MOV REG[222],0 (0102) mov reg[deh], 00h ; OscillatorControl_4 register (OSC_CR4)
0242: 62 DD 00 MOV REG[221],0 (0103) mov reg[ddh], 00h ; OscillatorGlobalBusEnableControl register (OSC_GO_EN)
0245: 62 D8 00 MOV REG[216],0 (0104) mov reg[d8h], 00h ; Port_0_MUXBusCtrl register (MUX_CR0)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -