adc10_1.h

CYPRESS的PSOC的AD转换编程

/*****************************************************************************
;;*****************************************************************************
;;  FILENAME:   ADC10_1.inc
;;  Version: 1.1, Updated on 2007/03/15 at 12:42:35
;;  Generated by PSoC Designer ver 4.4  b1884 : 14 Jan, 2007
;;
;;  DESCRIPTION:
;;    Assembler declarations for the ACDINC12 user module interface
;;    for the 22/24/27xxx PSoC family of devices.
;;-----------------------------------------------------------------------------
;;  Copyright (c) Cypress MicroSystems 2000-2003. All Rights Reserved.
;;*****************************************************************************
;;****************************************************************************/

#include <m8C.h>

// Function Fastcall Pragmas
#pragma fastcall16  ADC10_1_Start
#pragma fastcall16  ADC10_1_Stop
#pragma fastcall16  ADC10_1_StartADC
#pragma fastcall16  ADC10_1_StopADC
#pragma fastcall16  ADC10_1_fIsDataAvailable
#pragma fastcall16  ADC10_1_iGetData
#pragma fastcall16  ADC10_1_ClearFlag
#pragma fastcall16  ADC10_1_iGetDataClearFlag
#pragma fastcall16  ADC10_1_iCal


//-------------------------------------------------
// Prototypes of the ADC10 API.
//-------------------------------------------------
extern void ADC10_1_Start(BYTE bRange);
extern void ADC10_1_Stop(void);
extern void ADC10_1_StartADC(void);
extern void ADC10_1_StopADC(void);
extern BYTE ADC10_1_fIsDataAvailable(void);
extern int  ADC10_1_iGetData(void);
extern void ADC10_1_ClearFlag(void);
extern int  ADC10_1_iGetDataClearFlag(void);
extern int  ADC10_1_iCal(int iVal, BYTE bCalIn);


#define ADC10_1_LOWRANGE		0x01
#define ADC10_1_FULLRANGE  	0x03

#define ADC10_1_CAL_VBG		0x03
#define ADC10_1_CAL_AMUXBUS 	0x07
#define ADC10_1_CAL_P0_0		0x10
#define ADC10_1_CAL_P0_1		0x90
#define ADC10_1_CAL_P0_2		0x14
#define ADC10_1_CAL_P0_3		0x91
#define ADC10_1_CAL_P0_4		0x18
#define ADC10_1_CAL_P0_5		0x92
#define ADC10_1_CAL_P0_6		0x1C
#define ADC10_1_CAL_P0_7		0x93

// Counter Block Register Definitions
#pragma ioport  ADC10_1_ASE_CR0:    0x080
BYTE            ADC10_1_ASE_CR0;
#pragma ioport  ADC10_1_ACE_CR1:    0x072
BYTE            ADC10_1_ACE_CR1;
#pragma ioport  ADC10_1_ACE_CR2:    0x073
BYTE            ADC10_1_ACE_CR2;
#pragma ioport  ADC10_1_ADC_CR: 0x068
BYTE            ADC10_1_ADC_CR;
#pragma ioport  ADC10_1_ADC_TR: 0x1e5
BYTE            ADC10_1_ADC_TR;
 
// Counter Block Register Definitions
#pragma ioport  ADC10_1_CNT_FN: 0x120
BYTE            ADC10_1_CNT_FN;
#pragma ioport  ADC10_1_CNT_IN: 0x121
BYTE            ADC10_1_CNT_IN;
#pragma ioport  ADC10_1_CNT_OUT:    0x122
BYTE            ADC10_1_CNT_OUT;
#pragma ioport  ADC10_1_CNT_DR0:    0x020
BYTE            ADC10_1_CNT_DR0;
#pragma ioport  ADC10_1_CNT_DR1:    0x021
BYTE            ADC10_1_CNT_DR1;
#pragma ioport  ADC10_1_CNT_DR2:    0x022
BYTE            ADC10_1_CNT_DR2;
#pragma ioport  ADC10_1_CNT_CR0:    0x023
BYTE            ADC10_1_CNT_CR0;