psocconfigtbl.asm

CYPRESS的PSOC的AD转换编程

; Generated by PSoC Designer ver 4.4  b1884 : 14 Jan, 2007
;
include "m8c.inc"
;  Personalization tables 
export LoadConfigTBL_adc
AREA psoc_config(rom, rel)
LoadConfigTBL_adc:
;  Ordered Global Register values
	M8C_SetBank1
	mov	reg[00h], 20h		; Port_0_DriveMode_0 register (PRT0DM0)
	mov	reg[01h], dfh		; Port_0_DriveMode_1 register (PRT0DM1)
	M8C_SetBank0
	mov	reg[03h], dfh		; Port_0_DriveMode_2 register (PRT0DM2)
	mov	reg[02h], 20h		; Port_0_GlobalSelect register (PRT0GS)
	M8C_SetBank1
	mov	reg[02h], 00h		; Port_0_IntCtrl_0 register (PRT0IC0)
	mov	reg[03h], 00h		; Port_0_IntCtrl_1 register (PRT0IC1)
	M8C_SetBank0
	mov	reg[01h], 00h		; Port_0_IntEn register (PRT0IE)
	M8C_SetBank1
	mov	reg[04h], 00h		; Port_1_DriveMode_0 register (PRT1DM0)
	mov	reg[05h], ffh		; Port_1_DriveMode_1 register (PRT1DM1)
	M8C_SetBank0
	mov	reg[07h], ffh		; Port_1_DriveMode_2 register (PRT1DM2)
	mov	reg[06h], 00h		; Port_1_GlobalSelect register (PRT1GS)
	M8C_SetBank1
	mov	reg[06h], 00h		; Port_1_IntCtrl_0 register (PRT1IC0)
	mov	reg[07h], 00h		; Port_1_IntCtrl_1 register (PRT1IC1)
	M8C_SetBank0
	mov	reg[05h], 00h		; Port_1_IntEn register (PRT1IE)
	M8C_SetBank1
	mov	reg[08h], 00h		; Port_2_DriveMode_0 register (PRT2DM0)
	mov	reg[09h], ffh		; Port_2_DriveMode_1 register (PRT2DM1)
	M8C_SetBank0
	mov	reg[0bh], ffh		; Port_2_DriveMode_2 register (PRT2DM2)
	mov	reg[0ah], 00h		; Port_2_GlobalSelect register (PRT2GS)
	M8C_SetBank1
	mov	reg[0ah], 00h		; Port_2_IntCtrl_0 register (PRT2IC0)
	mov	reg[0bh], 00h		; Port_2_IntCtrl_1 register (PRT2IC1)
	M8C_SetBank0
	mov	reg[09h], 00h		; Port_2_IntEn register (PRT2IE)
	M8C_SetBank1
	mov	reg[0ch], 00h		; Port_3_DriveMode_0 register (PRT3DM0)
	mov	reg[0dh], 0fh		; Port_3_DriveMode_1 register (PRT3DM1)
	M8C_SetBank0
	mov	reg[0fh], 0fh		; Port_3_DriveMode_2 register (PRT3DM2)
	mov	reg[0eh], 00h		; Port_3_GlobalSelect register (PRT3GS)
	M8C_SetBank1
	mov	reg[0eh], 00h		; Port_3_IntCtrl_0 register (PRT3IC0)
	mov	reg[0fh], 00h		; Port_3_IntCtrl_1 register (PRT3IC1)
	M8C_SetBank0
	mov	reg[0dh], 00h		; Port_3_IntEn register (PRT3IE)
	M8C_SetBank0
;  Global Register values
	mov	reg[60h], 0bh		; AnalogColumnInputSelect register (AMX_IN)
	mov	reg[64h], 00h		; AnalogComparatorControl0 register (CMP_CR0)
	mov	reg[66h], 00h		; AnalogComparatorControl1 register (CMP_CR1)
	mov	reg[61h], 00h		; AnalogMuxBusConfig register (AMUXCFG)
	mov	reg[fdh], 00h		; DAC_Data register (DAC_D)
	mov	reg[e6h], 10h		; DecimatorControl_0 register (DEC_CR0)
	mov	reg[e7h], 00h		; DecimatorControl_1 register (DEC_CR1)
	mov	reg[d6h], 00h		; I2CConfig register (I2CCFG)
	mov	reg[62h], 00h		; PWM_Control register (PWM_CR)
	mov	reg[b0h], 00h		; Row_0_InputMux register (RDI0RI)
	mov	reg[b1h], 00h		; Row_0_InputSync register (RDI0SYN)
	mov	reg[b2h], 00h		; Row_0_LogicInputAMux register (RDI0IS)
	mov	reg[b3h], 33h		; Row_0_LogicSelect_0 register (RDI0LT0)
	mov	reg[b4h], 33h		; Row_0_LogicSelect_1 register (RDI0LT1)
	mov	reg[b5h], 20h		; Row_0_OutputDrive_0 register (RDI0SRO0)
	mov	reg[b6h], 00h		; Row_0_OutputDrive_1 register (RDI0SRO1)
;  Instance name ADC10_1, User Module ADC10
;       Instance name ADC10_1, Block Name ADC(ACE00)
	mov	reg[72h], 69h		;ADC10_1_ACE_CR1(ACE00CR1)
	mov	reg[73h], 00h		;ADC10_1_ACE_CR2(ACE00CR2)
;       Instance name ADC10_1, Block Name CNT(DBB00)
	mov	reg[23h], 00h		;ADC10_1_CNT_CR0(DBB00CR0)
	mov	reg[21h], 00h		;ADC10_1_CNT_DR1(DBB00DR1)
	mov	reg[22h], 00h		;ADC10_1_CNT_DR2(DBB00DR2)
;       Instance name ADC10_1, Block Name RAMP(ASE10)
	mov	reg[68h], 24h		;ADC10_1_ADC_CR(ADC0_CR)
	mov	reg[80h], 00h		;ADC10_1_ASE_CR0(ASE10CR0)
;  Instance name TX8_1, User Module TX8
;       Instance name TX8_1, Block Name TX8(DCB02)
	mov	reg[2bh], 00h		;TX8_1_CONTROL_REG  (DCB02CR0)
	mov	reg[29h], 00h		;TX8_1_TX_BUFFER_REG(DCB02DR1)
	mov	reg[2ah], 00h		;TX8_1_(DCB02DR2)
	M8C_SetBank1
;  Global Register values
	mov	reg[61h], 00h		; AnalogClockSelect1 register (CLK_CR1)
	mov	reg[60h], 00h		; AnalogColumnClockSelect register (CLK_CR0)
	mov	reg[62h], 00h		; AnalogIOControl_0 register (ABF_CR0)
	mov	reg[67h], 33h		; AnalogLUTControl0 register (ALT_CR0)
	mov	reg[64h], 00h		; ComparatorGlobalOutEn register (CMP_GO_EN)
	mov	reg[fdh], 00h		; DAC_Control register (DAC_CR)
	mov	reg[d1h], 00h		; GlobalDigitalInterconnect_Drive_Even_Input register (GDI_E_IN)
	mov	reg[d3h], 00h		; GlobalDigitalInterconnect_Drive_Even_Output register (GDI_E_OU)
	mov	reg[d0h], 00h		; GlobalDigitalInterconnect_Drive_Odd_Input register (GDI_O_IN)
	mov	reg[d2h], 00h		; GlobalDigitalInterconnect_Drive_Odd_Output register (GDI_O_OU)
	mov	reg[e1h], 00h		; OscillatorControl_1 register (OSC_CR1)
	mov	reg[e2h], 00h		; OscillatorControl_2 register (OSC_CR2)
	mov	reg[dfh], 00h		; OscillatorControl_3 register (OSC_CR3)
	mov	reg[deh], 00h		; OscillatorControl_4 register (OSC_CR4)
	mov	reg[ddh], 00h		; OscillatorGlobalBusEnableControl register (OSC_GO_EN)
	mov	reg[d8h], 00h		; Port_0_MUXBusCtrl register (MUX_CR0)
	mov	reg[d9h], 00h		; Port_1_MUXBusCtrl register (MUX_CR1)
	mov	reg[dah], 00h		; Port_2_MUXBusCtrl register (MUX_CR2)
	mov	reg[dbh], 00h		; Port_3_MUXBusCtrl register (MUX_CR3)
;  Instance name ADC10_1, User Module ADC10
;       Instance name ADC10_1, Block Name ADC(ACE00)
;       Instance name ADC10_1, Block Name CNT(DBB00)
	mov	reg[20h], 21h		;ADC10_1_CNT_FN(DBB00FN)
	mov	reg[21h], 45h		;ADC10_1_CNT_IN(DBB00IN)
	mov	reg[22h], 40h		;ADC10_1_CNT_OUT(DBB00OU)
;       Instance name ADC10_1, Block Name RAMP(ASE10)
	mov	reg[e5h], 00h		;ADC10_1_ADC_TR(ADC0_TR)
	mov	reg[63h], 00h		;ADC10_1_(AMD_CR0)
;  Instance name TX8_1, User Module TX8
;       Instance name TX8_1, Block Name TX8(DCB02)
	mov	reg[28h], 1dh		;TX8_1_FUNC_REG     (DCB02FN)
	mov	reg[29h], 06h		;TX8_1_INPUT_REG    (DCB02IN)
	mov	reg[2ah], 45h		;TX8_1_OUTPUT_REG   (DCB02OU)
	M8C_SetBank0
	ret


; PSoC Configuration file trailer PsocConfig.asm