📄 sa-1111.h
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#define SADRCS_RDSTB (1<<6)#define SADRCS_RBIU (1<<7)#define SAD_CS_DEN (1<<0)#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */#define SAD_CS_DSTA (1<<4)#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */#define SAD_CS_DSTB (1<<6)#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */#define SAITR_TFS (1<<0)#define SAITR_RFS (1<<1)#define SAITR_TUR (1<<2)#define SAITR_ROR (1<<3)#define SAITR_CADT (1<<4)#define SAITR_SADR (1<<5)#define SAITR_RSTO (1<<6)#define SAITR_TDBDA (1<<8)#define SAITR_TDBDB (1<<9)#define SAITR_RDBDA (1<<10)#define SAITR_RDBDB (1<<11)/* * General-Purpose I/O Interface * * Registers * PA_DDR GPIO Block A Data Direction * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write) * PA_SDR GPIO Block A Sleep Direction * PA_SSR GPIO Block A Sleep State * PB_DDR GPIO Block B Data Direction * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write) * PB_SDR GPIO Block B Sleep Direction * PB_SSR GPIO Block B Sleep State * PC_DDR GPIO Block C Data Direction * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write) * PC_SDR GPIO Block C Sleep Direction * PC_SSR GPIO Block C Sleep State */#define _PA_DDR _SA1111( 0x1000 )#define _PA_DRR _SA1111( 0x1004 )#define _PA_DWR _SA1111( 0x1004 )#define _PA_SDR _SA1111( 0x1008 )#define _PA_SSR _SA1111( 0x100c )#define _PB_DDR _SA1111( 0x1010 )#define _PB_DRR _SA1111( 0x1014 )#define _PB_DWR _SA1111( 0x1014 )#define _PB_SDR _SA1111( 0x1018 )#define _PB_SSR _SA1111( 0x101c )#define _PC_DDR _SA1111( 0x1020 )#define _PC_DRR _SA1111( 0x1024 )#define _PC_DWR _SA1111( 0x1024 )#define _PC_SDR _SA1111( 0x1028 )#define _PC_SSR _SA1111( 0x102c )#if LANGUAGE == C#define PA_DDR __CCREG(0x1000)#define PA_DRR __CCREG(0x1004)#define PA_DWR __CCREG(0x1004)#define PA_SDR __CCREG(0x1008)#define PA_SSR __CCREG(0x100c)#define PB_DDR __CCREG(0x1010)#define PB_DRR __CCREG(0x1014)#define PB_DWR __CCREG(0x1014)#define PB_SDR __CCREG(0x1018)#define PB_SSR __CCREG(0x101c)#define PC_DDR __CCREG(0x1020)#define PC_DRR __CCREG(0x1024)#define PC_DWR __CCREG(0x1024)#define PC_SDR __CCREG(0x1028)#define PC_SSR __CCREG(0x102c)#endif /* LANGUAGE == C *//* * Interrupt Controller * * Registers * INTTEST0 Test register 0 * INTTEST1 Test register 1 * INTEN0 Interrupt Enable register 0 * INTEN1 Interrupt Enable register 1 * INTPOL0 Interrupt Polarity selection 0 * INTPOL1 Interrupt Polarity selection 1 * INTTSTSEL Interrupt source selection * INTSTATCLR0 Interrupt Status/Clear 0 * INTSTATCLR1 Interrupt Status/Clear 1 * INTSET0 Interrupt source set 0 * INTSET1 Interrupt source set 1 * WAKE_EN0 Wake-up source enable 0 * WAKE_EN1 Wake-up source enable 1 * WAKE_POL0 Wake-up polarity selection 0 * WAKE_POL1 Wake-up polarity selection 1 */#define _INTTEST0 _SA1111( 0x1600 )#define _INTTEST1 _SA1111( 0x1604 )#define _INTEN0 _SA1111( 0x1608 )#define _INTEN1 _SA1111( 0x160c )#define _INTPOL0 _SA1111( 0x1610 )#define _INTPOL1 _SA1111( 0x1614 )#define _INTTSTSEL _SA1111( 0x1618 )#define _INTSTATCLR0 _SA1111( 0x161c )#define _INTSTATCLR1 _SA1111( 0x1620 )#define _INTSET0 _SA1111( 0x1624 )#define _INTSET1 _SA1111( 0x1628 )#define _WAKE_EN0 _SA1111( 0x162c )#define _WAKE_EN1 _SA1111( 0x1630 )#define _WAKE_POL0 _SA1111( 0x1634 )#define _WAKE_POL1 _SA1111( 0x1638 )#if LANGUAGE == C#define INTTEST0 __CCREG(0x1600)#define INTTEST1 __CCREG(0x1604)#define INTEN0 __CCREG(0x1608)#define INTEN1 __CCREG(0x160c)#define INTPOL0 __CCREG(0x1610)#define INTPOL1 __CCREG(0x1614)#define INTTSTSEL __CCREG(0x1618)#define INTSTATCLR0 __CCREG(0x161c)#define INTSTATCLR1 __CCREG(0x1620)#define INTSET0 __CCREG(0x1624)#define INTSET1 __CCREG(0x1628)#define WAKE_EN0 __CCREG(0x162c)#define WAKE_EN1 __CCREG(0x1630)#define WAKE_POL0 __CCREG(0x1634)#define WAKE_POL1 __CCREG(0x1638)#endif /* LANGUAGE == C *//* * PS/2 Trackpad and Mouse Interfaces * * Registers (prefix kbd applies to trackpad interface, mse to mouse) * KBDCR Control Register * KBDSTAT Status Register * KBDDATA Transmit/Receive Data register * KBDCLKDIV Clock Division Register * KBDPRECNT Clock Precount Register * KBDTEST1 Test register 1 * KBDTEST2 Test register 2 * KBDTEST3 Test register 3 * KBDTEST4 Test register 4 * MSECR * MSESTAT * MSEDATA * MSECLKDIV * MSEPRECNT * MSETEST1 * MSETEST2 * MSETEST3 * MSETEST4 * */#define _KBD( x ) _SA1111( 0x0A00 )#define _MSE( x ) _SA1111( 0x0C00 )#define _KBDCR _SA1111( 0x0A00 )#define _KBDSTAT _SA1111( 0x0A04 )#define _KBDDATA _SA1111( 0x0A08 )#define _KBDCLKDIV _SA1111( 0x0A0C )#define _KBDPRECNT _SA1111( 0x0A10 )#define _MSECR _SA1111( 0x0C00 )#define _MSESTAT _SA1111( 0x0C04 )#define _MSEDATA _SA1111( 0x0C08 )#define _MSECLKDIV _SA1111( 0x0C0C )#define _MSEPRECNT _SA1111( 0x0C10 )#if ( LANGUAGE == C )#define KBDCR __CCREG(0x0a00)#define KBDSTAT __CCREG(0x0a04)#define KBDDATA __CCREG(0x0a08)#define KBDCLKDIV __CCREG(0x0a0c)#define KBDPRECNT __CCREG(0x0a10)#define MSECR __CCREG(0x0c00)#define MSESTAT __CCREG(0x0c04)#define MSEDATA __CCREG(0x0c08)#define MSECLKDIV __CCREG(0x0c0c)#define MSEPRECNT __CCREG(0x0c10)#define KBDCR_ENA 0x08#define KBDCR_FKD 0x02#define KBDCR_FKC 0x01#define KBDSTAT_TXE 0x80#define KBDSTAT_TXB 0x40#define KBDSTAT_RXF 0x20#define KBDSTAT_RXB 0x10#define KBDSTAT_ENA 0x08#define KBDSTAT_RXP 0x04#define KBDSTAT_KBD 0x02#define KBDSTAT_KBC 0x01#define KBDCLKDIV_DivVal Fld(4,0)#define MSECR_ENA 0x08#define MSECR_FKD 0x02#define MSECR_FKC 0x01#define MSESTAT_TXE 0x80#define MSESTAT_TXB 0x40#define MSESTAT_RXF 0x20#define MSESTAT_RXB 0x10#define MSESTAT_ENA 0x08#define MSESTAT_RXP 0x04#define MSESTAT_MSD 0x02#define MSESTAT_MSC 0x01#define MSECLKDIV_DivVal Fld(4,0)#define KBDTEST1_CD 0x80#define KBDTEST1_RC1 0x40#define KBDTEST1_MC 0x20#define KBDTEST1_C Fld(2,3)#define KBDTEST1_T2 0x40#define KBDTEST1_T1 0x20#define KBDTEST1_T0 0x10#define KBDTEST2_TICBnRES 0x08#define KBDTEST2_RKC 0x04#define KBDTEST2_RKD 0x02#define KBDTEST2_SEL 0x01#define KBDTEST3_ms_16 0x80#define KBDTEST3_us_64 0x40#define KBDTEST3_us_16 0x20#define KBDTEST3_DIV8 0x10#define KBDTEST3_DIn 0x08#define KBDTEST3_CIn 0x04#define KBDTEST3_KD 0x02#define KBDTEST3_KC 0x01#define KBDTEST4_BC12 0x80#define KBDTEST4_BC11 0x40#define KBDTEST4_TRES 0x20#define KBDTEST4_CLKOE 0x10#define KBDTEST4_CRES 0x08#define KBDTEST4_RXB 0x04#define KBDTEST4_TXB 0x02#define KBDTEST4_SRX 0x01#define MSETEST1_CD 0x80#define MSETEST1_RC1 0x40#define MSETEST1_MC 0x20#define MSETEST1_C Fld(2,3)#define MSETEST1_T2 0x40#define MSETEST1_T1 0x20#define MSETEST1_T0 0x10#define MSETEST2_TICBnRES 0x08#define MSETEST2_RKC 0x04#define MSETEST2_RKD 0x02#define MSETEST2_SEL 0x01#define MSETEST3_ms_16 0x80#define MSETEST3_us_64 0x40#define MSETEST3_us_16 0x20#define MSETEST3_DIV8 0x10#define MSETEST3_DIn 0x08#define MSETEST3_CIn 0x04#define MSETEST3_KD 0x02#define MSETEST3_KC 0x01#define MSETEST4_BC12 0x80#define MSETEST4_BC11 0x40#define MSETEST4_TRES 0x20#define MSETEST4_CLKOE 0x10#define MSETEST4_CRES 0x08#define MSETEST4_RXB 0x04#define MSETEST4_TXB 0x02#define MSETEST4_SRX 0x01#endif /* LANGUAGE == C *//* * PCMCIA Interface * * Registers * PCSR Status Register * PCCR Control Register * PCSSR Sleep State Register */#define _PCCR _SA1111( 0x1800 )#define _PCSSR _SA1111( 0x1804 )#define _PCSR _SA1111( 0x1808 )#if LANGUAGE == C#define PCCR __CCREG(0x1800)#define PCSSR __CCREG(0x1804)#define PCSR __CCREG(0x1808)#endif /* LANGUAGE == C */#define PCSR_S0_READY (1<<0)#define PCSR_S1_READY (1<<1)#define PCSR_S0_DETECT (1<<2)#define PCSR_S1_DETECT (1<<3)#define PCSR_S0_VS1 (1<<4)#define PCSR_S0_VS2 (1<<5)#define PCSR_S1_VS1 (1<<6)#define PCSR_S1_VS2 (1<<7)#define PCSR_S0_WP (1<<8)#define PCSR_S1_WP (1<<9)#define PCSR_S0_BVD1 (1<<10)#define PCSR_S0_BVD2 (1<<11)#define PCSR_S1_BVD1 (1<<12)#define PCSR_S1_BVD2 (1<<13)#define PCCR_S0_RST (1<<0)#define PCCR_S1_RST (1<<1)#define PCCR_S0_FLT (1<<2)#define PCCR_S1_FLT (1<<3)#define PCCR_S0_PWAITEN (1<<4)#define PCCR_S1_PWAITEN (1<<5)#define PCCR_S0_PSE (1<<6)#define PCCR_S1_PSE (1<<7)#define PCSSR_S0_SLEEP (1<<0)#define PCSSR_S1_SLEEP (1<<1)#endif /* _ASM_ARCH_SA1111 */⌨️ 快捷键说明
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