📄 sa-1111.h
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/* * linux/include/asm/arch/SA-1111.h * * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu> * * This file contains definitions for the SA-1111 Companion Chip. * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) * */#ifndef _ASM_ARCH_SA1111#define _ASM_ARCH_SA1111#include <asm/arch/bitfield.h>/* * Macro that calculates real address for registers in the SA-1111 */#define _SA1111( x ) ((x) + SA1111_BASE)/* * 26 bits of the SA-1110 address bus are available to the SA-1111. * Use these when feeding target addresses to the DMA engines. */#define SA1111_ADDR_WIDTH (26)#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)/* * Don't ask the (SAC) DMA engines to move less than this amount. */#define SA1111_SAC_DMA_MIN_XFER (0x800)/* * SA1111 register definitions. */#define __CCREG(x) __REGP(SA1111_VBASE + (x))/* System Bus Interface (SBI) * * Registers * SKCR Control Register * SMCR Shared Memory Controller Register * SKID ID Register */#define _SBI_SKCR _SA1111(0x0000)#define _SBI_SMCR _SA1111(0x0004)#define _SBI_SKID _SA1111(0x0008)#if LANGUAGE == C#define SBI_SKCR __CCREG(0x0000)#define SBI_SMCR __CCREG(0x0004)#define SBI_SKID __CCREG(0x0008)#endif /* LANGUAGE == C */#define SKCR_PLL_BYPASS (1<<0)#define SKCR_RCLKEN (1<<1)#define SKCR_SLEEP (1<<2)#define SKCR_DOZE (1<<3)#define SKCR_VCO_OFF (1<<4)#define SKCR_SCANTSTEN (1<<5)#define SKCR_CLKTSTEN (1<<6)#define SKCR_RDYEN (1<<7)#define SKCR_SELAC (1<<8)#define SKCR_OPPC (1<<9)#define SKCR_PLLTSTEN (1<<10)#define SKCR_USBIOTSTEN (1<<11)/* * Don't believe the specs! Take them, throw them outside. Leave them * there for a week. Spit on them. Walk on them. Stamp on them. * Pour gasoline over them and finally burn them. Now think about coding. * - The October 1999 errata (278260-007) says its bit 13, 1 to enable. * - The Feb 2001 errata (278260-010) says that the previous errata * (278260-009) is wrong, and its bit actually 12, fixed in spec * 278242-003. * - The SA1111 manual (278242) says bit 12, but 0 to enable. * - Reality is bit 13, 1 to enable. * -- rmk */#define SKCR_OE_EN (1<<13)#define SMCR_DTIM (1<<0)#define SMCR_MBGE (1<<1)#define SMCR_DRAC_0 (1<<2)#define SMCR_DRAC_1 (1<<3)#define SMCR_DRAC_2 (1<<4)#define SMCR_DRAC Fld(3, 2)#define SMCR_CLAT (1<<5)#define SKID_SIREV_MASK (0x000000f0)#define SKID_MTREV_MASK (0x0000000f)#define SKID_ID_MASK (0xffffff00)#define SKID_SA1111_ID (0x690cc200)/* * System Controller * * Registers * SKPCR Power Control Register * SKCDR Clock Divider Register * SKAUD Audio Clock Divider Register * SKPMC PS/2 Mouse Clock Divider Register * SKPTC PS/2 Track Pad Clock Divider Register * SKPEN0 PWM0 Enable Register * SKPWM0 PWM0 Clock Register * SKPEN1 PWM1 Enable Register * SKPWM1 PWM1 Clock Register */#define _SKPCR _SA1111(0x0200)#define _SKCDR _SA1111(0x0204)#define _SKAUD _SA1111(0x0208)#define _SKPMC _SA1111(0x020c)#define _SKPTC _SA1111(0x0210)#define _SKPEN0 _SA1111(0x0214)#define _SKPWM0 _SA1111(0x0218)#define _SKPEN1 _SA1111(0x021c)#define _SKPWM1 _SA1111(0x0220)#if LANGUAGE == C#define SKPCR __CCREG(0x0200)#define SKCDR __CCREG(0x0204)#define SKAUD __CCREG(0x0208)#define SKPMC __CCREG(0x020c)#define SKPTC __CCREG(0x0210)#define SKPEN0 __CCREG(0x0214)#define SKPWM0 __CCREG(0x0218)#define SKPEN1 __CCREG(0x021c)#define SKPWM1 __CCREG(0x0220)#endif /* LANGUAGE == C */#define SKPCR_UCLKEN (1<<0)#define SKPCR_ACCLKEN (1<<1)#define SKPCR_I2SCLKEN (1<<2)#define SKPCR_L3CLKEN (1<<3)#define SKPCR_SCLKEN (1<<4)#define SKPCR_PMCLKEN (1<<5)#define SKPCR_PTCLKEN (1<<6)#define SKPCR_DCLKEN (1<<7)#define SKPCR_PWMCLKEN (1<<8)/* * USB Host controller */#define _USB_OHCI_OP_BASE _SA1111( 0x400 )#define _USB_STATUS _SA1111( 0x518 )#define _USB_RESET _SA1111( 0x51c )#define _USB_INTERRUPTEST _SA1111( 0x520 )#define _USB_EXTENT (_USB_INTERRUPTEST - _USB_OHCI_OP_BASE + 4)#if LANGUAGE == C#define USB_OHCI_OP_BASE __CCREG(0x0400)#define USB_STATUS __CCREG(0x0518)#define USB_RESET __CCREG(0x051c)#define USB_INTERRUPTEST __CCReG(0x0520)#endif /* LANGUAGE == C */#define USB_RESET_FORCEIFRESET (1 << 0)#define USB_RESET_FORCEHCRESET (1 << 1)#define USB_RESET_CLKGENRESET (1 << 2)#define USB_RESET_SIMSCALEDOWN (1 << 3)#define USB_RESET_USBINTTEST (1 << 4)#define USB_RESET_SLEEPSTBYEN (1 << 5)#define USB_RESET_PWRSENSELOW (1 << 6)#define USB_RESET_PWRCTRLLOW (1 << 7)/* * Serial Audio Controller * * Registers * SACR0 Serial Audio Common Control Register * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register * SACR2 Serial Audio AC-link Control Register * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register * SASR1 Serial Audio AC-link Interface & FIFO Status Register * SASCR Serial Audio Status Clear Register * L3_CAR L3 Control Bus Address Register * L3_CDR L3 Control Bus Data Register * ACCAR AC-link Command Address Register * ACCDR AC-link Command Data Register * ACSAR AC-link Status Address Register * ACSDR AC-link Status Data Register * SADTCS Serial Audio DMA Transmit Control/Status Register * SADTSA Serial Audio DMA Transmit Buffer Start Address A * SADTCA Serial Audio DMA Transmit Buffer Count Register A * SADTSB Serial Audio DMA Transmit Buffer Start Address B * SADTCB Serial Audio DMA Transmit Buffer Count Register B * SADRCS Serial Audio DMA Receive Control/Status Register * SADRSA Serial Audio DMA Receive Buffer Start Address A * SADRCA Serial Audio DMA Receive Buffer Count Register A * SADRSB Serial Audio DMA Receive Buffer Start Address B * SADRCB Serial Audio DMA Receive Buffer Count Register B * SAITR Serial Audio Interrupt Test Register * SADR Serial Audio Data Register (16 x 32-bit) */#define _SACR0 _SA1111( 0x0600 )#define _SACR1 _SA1111( 0x0604 )#define _SACR2 _SA1111( 0x0608 )#define _SASR0 _SA1111( 0x060c )#define _SASR1 _SA1111( 0x0610 )#define _SASCR _SA1111( 0x0618 )#define _L3_CAR _SA1111( 0x061c )#define _L3_CDR _SA1111( 0x0620 )#define _ACCAR _SA1111( 0x0624 )#define _ACCDR _SA1111( 0x0628 )#define _ACSAR _SA1111( 0x062c )#define _ACSDR _SA1111( 0x0630 )#define _SADTCS _SA1111( 0x0634 )#define _SADTSA _SA1111( 0x0638 )#define _SADTCA _SA1111( 0x063c )#define _SADTSB _SA1111( 0x0640 )#define _SADTCB _SA1111( 0x0644 )#define _SADRCS _SA1111( 0x0648 )#define _SADRSA _SA1111( 0x064c )#define _SADRCA _SA1111( 0x0650 )#define _SADRSB _SA1111( 0x0654 )#define _SADRCB _SA1111( 0x0658 )#define _SAITR _SA1111( 0x065c )#define _SADR _SA1111( 0x0680 )#if LANGUAGE == C#define SACR0 __CCREG(0x0600)#define SACR1 __CCREG(0x0604)#define SACR2 __CCREG(0x0608)#define SASR0 __CCREG(0x060c)#define SASR1 __CCREG(0x0610)#define SASCR __CCREG(0x0618)#define L3_CAR __CCREG(0x061c)#define L3_CDR __CCREG(0x0620)#define ACCAR __CCREG(0x0624)#define ACCDR __CCREG(0x0628)#define ACSAR __CCREG(0x062c)#define ACSDR __CCREG(0x0630)#define SADTCS __CCREG(0x0634)#define SADTSA __CCREG(0x0638)#define SADTCA __CCREG(0x063c)#define SADTSB __CCREG(0x0640)#define SADTCB __CCREG(0x0644)#define SADRCS __CCREG(0x0648)#define SADRSA __CCREG(0x064c)#define SADRCA __CCREG(0x0650)#define SADRSB __CCREG(0x0654)#define SADRCB __CCREG(0x0658)#define SAITR __CCREG(0x065c)#define SADR __CCREG(0x0680)#endif /* LANGUAGE == C */#define SACR0_ENB (1<<0)#define SACR0_BCKD (1<<2)#define SACR0_RST (1<<3)#define SACR1_AMSL (1<<0)#define SACR1_L3EN (1<<1)#define SACR1_L3MB (1<<2)#define SACR1_DREC (1<<3)#define SACR1_DRPL (1<<4)#define SACR1_ENLBF (1<<5)#define SACR2_TS3V (1<<0)#define SACR2_TS4V (1<<1)#define SACR2_WKUP (1<<2)#define SACR2_DREC (1<<3)#define SACR2_DRPL (1<<4)#define SACR2_ENLBF (1<<5)#define SACR2_RESET (1<<6)#define SASR0_TNF (1<<0)#define SASR0_RNE (1<<1)#define SASR0_BSY (1<<2)#define SASR0_TFS (1<<3)#define SASR0_RFS (1<<4)#define SASR0_TUR (1<<5)#define SASR0_ROR (1<<6)#define SASR0_L3WD (1<<16)#define SASR0_L3RD (1<<17)#define SASR1_TNF (1<<0)#define SASR1_RNE (1<<1)#define SASR1_BSY (1<<2)#define SASR1_TFS (1<<3)#define SASR1_RFS (1<<4)#define SASR1_TUR (1<<5)#define SASR1_ROR (1<<6)#define SASR1_CADT (1<<16)#define SASR1_SADR (1<<17)#define SASR1_RSTO (1<<18)#define SASR1_CLPM (1<<19)#define SASR1_CRDY (1<<20)#define SASR1_RS3V (1<<21)#define SASR1_RS4V (1<<22)#define SASCR_TUR (1<<5)#define SASCR_ROR (1<<6)#define SASCR_DTS (1<<16)#define SASCR_RDD (1<<17)#define SASCR_STO (1<<18)#define SADTCS_TDEN (1<<0)#define SADTCS_TDIE (1<<1)#define SADTCS_TDBDA (1<<3)#define SADTCS_TDSTA (1<<4)#define SADTCS_TDBDB (1<<5)#define SADTCS_TDSTB (1<<6)#define SADTCS_TBIU (1<<7)#define SADRCS_RDEN (1<<0)#define SADRCS_RDIE (1<<1)#define SADRCS_RDBDA (1<<3)#define SADRCS_RDSTA (1<<4)#define SADRCS_RDBDB (1<<5)⌨️ 快捷键说明
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