init.c

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

			SiS_SetReg1 (SiS_P3c4, 0x14,
				     (USHORT) ((data & 0xFD) | 0x01));
		}
		return;

	} else {
		/* DDR Dual channel */
		SiS_SetReg1 (SiS_P3c4, 0x13, 0x00);
		SiS_SetReg1 (SiS_P3c4, 0x14, 0x02);	/* Channel A, 64bit */
		/* should delay */
		SiS_DDR_MRS ();

		SiS_ChannelAB = 0;
		SiS_DataBusWidth = 64;
		pVideoMemory[0] = 0x01234567L;
		pVideoMemory[1] = 0x456789ABL;
		pVideoMemory[2] = 0x89ABCDEFL;
		pVideoMemory[3] = 0xCDEF0123L;
		pVideoMemory[4] = 0x55555555L;
		pVideoMemory[5] = 0x55555555L;
		pVideoMemory[6] = 0xAAAAAAAAL;
		pVideoMemory[7] = 0xAAAAAAAAL;

		if (pVideoMemory[1] == 0x456789ABL) {
			if (pVideoMemory[0] == 0x01234567L) {
				/* Channel A 64bit */
				return;
			}
		} else {
			if (pVideoMemory[0] == 0x01234567L) {
				/* Channel A 32bit */
				SiS_DataBusWidth = 32;
				SiS_SetReg1 (SiS_P3c4, 0x14, 0x00);
				return;
			}

		}

		SiS_SetReg1 (SiS_P3c4, 0x14, 0x03);	/* Channel B, 64bit */
		SiS_DDR_MRS ();

		SiS_ChannelAB = 1;
		SiS_DataBusWidth = 64;
		pVideoMemory[0] = 0x01234567L;
		pVideoMemory[1] = 0x456789ABL;
		pVideoMemory[2] = 0x89ABCDEFL;
		pVideoMemory[3] = 0xCDEF0123L;
		pVideoMemory[4] = 0x55555555L;
		pVideoMemory[5] = 0x55555555L;
		pVideoMemory[6] = 0xAAAAAAAAL;
		pVideoMemory[7] = 0xAAAAAAAAL;
		if (pVideoMemory[1] == 0x456789ABL) {
			/* Channel B 64 */
			if (pVideoMemory[0] == 0x01234567L) {
				/* Channel B 64bit */
				return;
			} else {
				/* error */
			}
		} else {
			if (pVideoMemory[0] == 0x01234567L) {
				/* Channel B 32 */
				SiS_DataBusWidth = 32;
				SiS_SetReg1 (SiS_P3c4, 0x14, 0x01);
			} else {
				/* error */
			}
		}
	}
}

int
SiS_SetRank (int index, UCHAR RankNo, UCHAR SiS_ChannelAB,
	     USHORT DRAMTYPE_TABLE[][5])
{
	USHORT data;
	int RankSize;

	if ((RankNo == 2) && (DRAMTYPE_TABLE[index][0] == 2))
		return 0;

	RankSize = DRAMTYPE_TABLE[index][3] / 2 * SiS_DataBusWidth / 32;

	if (RankNo * RankSize <= 128) {
		data = 0;
		while ((RankSize >>= 1) > 0) {
			data += 0x10;
		}
		data |= (RankNo - 1) << 2;
		data |= (SiS_DataBusWidth / 64) & 2;
		data |= SiS_ChannelAB;
		SiS_SetReg1 (SiS_P3c4, 0x14, data);
		/* should delay */
		SiS_SDR_MRS ();
		return 1;
	} else
		return 0;

}

int
SiS_SetDDRChannel (int index, UCHAR ChannelNo, UCHAR SiS_ChannelAB,
		   USHORT DRAMTYPE_TABLE[][5])
{
	USHORT data;
	int RankSize;

	RankSize = DRAMTYPE_TABLE[index][3] / 2 * SiS_DataBusWidth / 32;
	/* RankSize = DRAMTYPE_TABLE[index][3]; */
	if (ChannelNo * RankSize <= 128) {
		data = 0;
		while ((RankSize >>= 1) > 0) {
			data += 0x10;
		}
		if (ChannelNo == 2)
			data |= 0x0C;

		data |= (SiS_DataBusWidth / 32) & 2;
		data |= SiS_ChannelAB;
		SiS_SetReg1 (SiS_P3c4, 0x14, data);
		/* should delay */
		SiS_DDR_MRS ();
		return 1;
	} else
		return 0;

}

int
SiS_CheckColumn (int index, USHORT DRAMTYPE_TABLE[][5], ULONG FBAddress)
{
	int i;
	ULONG Increment, Position;

	/*Increment = 1<<(DRAMTYPE_TABLE[index][2] + SiS_DataBusWidth / 64 + 1); */
	Increment = 1 << (10 + SiS_DataBusWidth / 64);

	for (i = 0, Position = 0; i < 2; i++) {
		*((PULONG) (FBAddress + Position)) = Position;
		Position += Increment;
	}

	for (i = 0, Position = 0; i < 2; i++) {
/*    if (FBAddress[Position]!=Position) */
		if ((*(PULONG) (FBAddress + Position)) != Position)
			return 0;
		Position += Increment;
	}
	return 1;
}

int
SiS_CheckBanks (int index, USHORT DRAMTYPE_TABLE[][5], ULONG FBAddress)
{
	int i;
	ULONG Increment, Position;
	Increment = 1 << (DRAMTYPE_TABLE[index][2] + SiS_DataBusWidth / 64 + 2);

	for (i = 0, Position = 0; i < 4; i++) {
/*    FBAddress[Position]=Position; */
		*((PULONG) (FBAddress + Position)) = Position;
		Position += Increment;
	}

	for (i = 0, Position = 0; i < 4; i++) {
/*    if (FBAddress[Position]!=Position) */
		if ((*(PULONG) (FBAddress + Position)) != Position)
			return 0;
		Position += Increment;
	}
	return 1;
}

int
SiS_CheckRank (int RankNo, int index, USHORT DRAMTYPE_TABLE[][5],
	       ULONG FBAddress)
{
	int i;
	ULONG Increment, Position;
	Increment = 1 << (DRAMTYPE_TABLE[index][2] + DRAMTYPE_TABLE[index][1] +
			  DRAMTYPE_TABLE[index][0] + SiS_DataBusWidth / 64 +
			  RankNo);

	for (i = 0, Position = 0; i < 2; i++) {
/*    FBAddress[Position]=Position; */
		*((PULONG) (FBAddress + Position)) = Position;
		/* *((PULONG)(FBAddress))=Position; */
		Position += Increment;
	}

	for (i = 0, Position = 0; i < 2; i++) {
/*    if (FBAddress[Position]!=Position) */
		if ((*(PULONG) (FBAddress + Position)) != Position)
			/*if ( (*(PULONG) (FBAddress )) !=Position) */
			return 0;
		Position += Increment;
	}
	return 1;

}

int
SiS_CheckDDRRank (int RankNo, int index, USHORT DRAMTYPE_TABLE[][5],
		  ULONG FBAddress)
{
	ULONG Increment, Position;
	USHORT data;

	Increment = 1 << (DRAMTYPE_TABLE[index][2] + DRAMTYPE_TABLE[index][1] +
			  DRAMTYPE_TABLE[index][0] + SiS_DataBusWidth / 64 +
			  RankNo);

	Increment += Increment / 2;

	Position = 0;
	*((PULONG) (FBAddress + Position + 0)) = 0x01234567;
	*((PULONG) (FBAddress + Position + 1)) = 0x456789AB;
	*((PULONG) (FBAddress + Position + 2)) = 0x55555555;
	*((PULONG) (FBAddress + Position + 3)) = 0x55555555;
	*((PULONG) (FBAddress + Position + 4)) = 0xAAAAAAAA;
	*((PULONG) (FBAddress + Position + 5)) = 0xAAAAAAAA;

	if ((*(PULONG) (FBAddress + 1)) == 0x456789AB)
		return 1;

	if ((*(PULONG) (FBAddress + 0)) == 0x01234567)
		return 0;

	data = SiS_GetReg1 (SiS_P3c4, 0x14);
	data &= 0xF3;
	data |= 0x08;
	SiS_SetReg1 (SiS_P3c4, 0x14, data);
	data = SiS_GetReg1 (SiS_P3c4, 0x15);
	data += 0x20;
	SiS_SetReg1 (SiS_P3c4, 0x15, data);

	return 1;

}

int
SiS_CheckRanks (int RankNo, int index, USHORT DRAMTYPE_TABLE[][5],
		ULONG FBAddress)
{
	int r;

	for (r = RankNo; r >= 1; r--) {
		if (!SiS_CheckRank (r, index, DRAMTYPE_TABLE, FBAddress))
			return 0;
	}
	if (!SiS_CheckBanks (index, DRAMTYPE_TABLE, FBAddress))
		return 0;

	if (!SiS_CheckColumn (index, DRAMTYPE_TABLE, FBAddress))
		return 0;
	return 1;

}

int
SiS_CheckDDRRanks (int RankNo, int index, USHORT DRAMTYPE_TABLE[][5],
		   ULONG FBAddress)
{
	int r;

	for (r = RankNo; r >= 1; r--) {
		if (!SiS_CheckDDRRank (r, index, DRAMTYPE_TABLE, FBAddress))
			return 0;
	}
	if (!SiS_CheckBanks (index, DRAMTYPE_TABLE, FBAddress))
		return 0;

	if (!SiS_CheckColumn (index, DRAMTYPE_TABLE, FBAddress))
		return 0;
	return 1;

}

int
SiS_SDRSizing (ULONG FBAddress)
{
	int i;
	UCHAR j;

	for (i = 0; i < 13; i++) {
		SiS_SetDRAMSizingType (i, SiS_SDRDRAM_TYPE);
		for (j = 2; j > 0; j--) {

			if (!SiS_SetRank
			    (i, (UCHAR) j, SiS_ChannelAB,
			     SiS_SDRDRAM_TYPE)) continue;
			else {
				if (SiS_CheckRanks
				    (j, i, SiS_SDRDRAM_TYPE,
				     FBAddress)) return 1;
			}
		}
	}
	return 0;
}

int
SiS_DDRSizing (ULONG FBAddress)
{

	int i;
	UCHAR j;

	for (i = 0; i < 4; i++) {
		SiS_SetDRAMSizingType (i, SiS_DDRDRAM_TYPE);
		SiS_DisableChannelInterleaving (i, SiS_DDRDRAM_TYPE);
		for (j = 2; j > 0; j--) {
			SiS_SetDDRChannel (i, j, SiS_ChannelAB,
					   SiS_DDRDRAM_TYPE);
			if (!SiS_SetRank
			    (i, (UCHAR) j, SiS_ChannelAB,
			     SiS_DDRDRAM_TYPE)) continue;
			else {
				if (SiS_CheckDDRRanks
				    (j, i, SiS_DDRDRAM_TYPE,
				     FBAddress)) return 1;
			}
		}
	}
	return 0;
}

/*

 check if read cache pointer is correct

*/
void
SiS_VerifyMclk (ULONG FBAddr)
{
	PUCHAR pVideoMemory = (PUCHAR) FBAddr;
	UCHAR i, j;
	USHORT Temp, SR21;

	pVideoMemory[0] = 0xaa;	/* alan */
	pVideoMemory[16] = 0x55;	/* note: PCI read cache is off */

	if ((pVideoMemory[0] != 0xaa) || (pVideoMemory[16] != 0x55)) {
		for (i = 0, j = 16; i < 2; i++, j += 16) {
			SR21 = SiS_GetReg1 (SiS_P3c4, 0x21);
			Temp = SR21 & 0xFB;	/* disable PCI post write buffer empty gating */
			SiS_SetReg1 (SiS_P3c4, 0x21, Temp);

			Temp = SiS_GetReg1 (SiS_P3c4, 0x3C);
			Temp = Temp | 0x01;	/*MCLK reset */
			SiS_SetReg1 (SiS_P3c4, 0x3C, Temp);
			Temp = SiS_GetReg1 (SiS_P3c4, 0x3C);
			Temp = Temp & 0xFE;	/* MCLK normal operation */
			SiS_SetReg1 (SiS_P3c4, 0x3C, Temp);
			SiS_SetReg1 (SiS_P3c4, 0x21, SR21);

			pVideoMemory[16 + j] = j;
			if (pVideoMemory[16 + j] == j) {
				pVideoMemory[j] = j;
				break;
			}
		}
	}

}

int
Is315E (void)
{
	USHORT data;

	data = SiS_GetReg1 (SiS_P3d4, 0x5F);
	if (data & 0x10)
		return 1;
	else
		return 0;
}

void
SiS_SetDRAMSize_310 (PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
	ULONG ROMAddr = (ULONG) HwDeviceExtension->pjVirtualRomBase;
	ULONG FBAddr = (ULONG) HwDeviceExtension->pjVideoMemoryAddress;
	/*USHORT  BaseAddr = (USHORT)HwDeviceExtension->ulIOAddress; */
	USHORT data;

#ifdef SIS301
	/*SiS_SetReg1(SiS_P3d4,0x30,0x40);   */
#endif
#ifdef SIS302
	SiS_SetReg1 (SiS_P3d4, 0x30, 0x4D);	/* alan,should change value */
	SiS_SetReg1 (SiS_P3d4, 0x31, 0xc0);	/* alan,should change value */
	SiS_SetReg1 (SiS_P3d4, 0x34, 0x3F);	/* alan,should change value */
#endif

	SiSSetMode (HwDeviceExtension, 0x2e);

	data = SiS_GetReg1 (SiS_P3c4, 0x21);
	SiS_SetReg1 (SiS_P3c4, 0x21, (USHORT) (data & 0xDF));	/* disable read cache */

	data = SiS_GetReg1 (SiS_P3c4, 0x1);
	data = data | 0x20;
	SiS_SetReg1 (SiS_P3c4, 0x01, data);	/* Turn OFF Display */

	data = SiS_GetReg1 (SiS_P3c4, 0x16);
	SiS_SetReg1 (SiS_P3c4, 0x16, (USHORT) (data | 0x0F));	/* assume lowest speed DRAM */

	SiS_SetDRAMModeRegister (ROMAddr);
	SiS_DisableRefresh ();
	SiS_CheckBusWidth_310 (ROMAddr, FBAddr);

	SiS_VerifyMclk (FBAddr);	/* alan 2000/7/3 */

	if (SiS_Get310DRAMType (ROMAddr) < 2) {
		SiS_SDRSizing (FBAddr);
	} else {
		SiS_DDRSizing (FBAddr);
	}

	if (Is315E ()) {
		data = SiS_GetReg1 (SiS_P3c4, 0x14);
		if ((data & 0x0C) == 0x0C) {	/* dual channel */
			if ((data & 0xF0) > 0x40)
				data = (data & 0x0F) | 0x40;
		} else {	/* single channel */

			if ((data & 0xF0) > 0x50)
				data = (data & 0x0F) | 0x50;
		}

	}

	SiS_SetReg1 (SiS_P3c4, 0x16, SiS_SR15[1][SiS_RAMType]);	/* restore SR16 */

	SiS_EnableRefresh (ROMAddr);
	data = SiS_GetReg1 (SiS_P3c4, 0x21);