init.c

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

	return (TRUE);
}

void
SiS_Set_LVDS_TRUMPION (PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
	USHORT temp;

#ifdef CONFIG_FB_SIS_300
	if ((HwDeviceExtension->jChipType == SIS_540) ||
	    (HwDeviceExtension->jChipType == SIS_630) ||
	    (HwDeviceExtension->jChipType == SIS_730)) {
		temp = (UCHAR) SiS_GetReg1 (SiS_P3c4, 0x1A);
		temp = (temp & 0xE0) >> 4;
		SiS_SetRegANDOR (SiS_P3d4, 0x37, 0xF1, temp);
		temp = temp >> 1;
		if ((temp == 0) || (temp == 1)) {	/* for 301 */
			SiS_IF_DEF_LVDS = 0;
			SiS_IF_DEF_CH7005 = 0;
			SiS_IF_DEF_TRUMPION = 0;
		}
		if ((temp >= 2) && (temp <= 5)) {
			SiS_IF_DEF_LVDS = 1;
		}
		if (temp == 3)
			SiS_IF_DEF_TRUMPION = 1;
		if ((temp == 4) || (temp == 5))
			SiS_IF_DEF_CH7005 = 1;
	} else {
		SiS_IF_DEF_LVDS = 0;
		SiS_IF_DEF_TRUMPION = 0;
		SiS_IF_DEF_CH7005 = 0;
	}
#else
	if ((HwDeviceExtension->jChipType == SIS_550) ||
	    (HwDeviceExtension->jChipType == SIS_640) ||	/* 08/20/01 chiawen for 640/740 */
	    (HwDeviceExtension->jChipType == SIS_740))
	 {			/* 09/03/01 chiawen for 650 */
		SiS_IF_DEF_LVDS = 0;
		SiS_IF_DEF_TRUMPION = 0;
		SiS_IF_DEF_CH7005 = 0;
	}
#endif
}

/* ===============  for 300 dram sizing begin  =============== */
#ifdef CONFIG_FB_SIS_300
void
SiS_SetDRAMSize_300 (PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
	/*ULONG   ROMAddr  = (ULONG)HwDeviceExtension->pjVirtualRomBase; */
	ULONG FBAddr = (ULONG) HwDeviceExtension->pjVideoMemoryAddress;
	/*USHORT  BaseAddr = (USHORT)HwDeviceExtension->ulIOAddress; */
	USHORT SR13, SR14 = 0, buswidth, Done;
	SHORT i, j, k;
	USHORT data, TotalCapacity, PhysicalAdrOtherPage = 0;
	ULONG Addr;
	UCHAR temp;

	int PseudoRankCapacity, PseudoTotalCapacity, PseudoAdrPinCount;
	int RankCapacity, AdrPinCount, BankNumHigh, BankNumMid, MB2Bank;
	/*int PageCapacity,PhysicalAdrHigh,PhysicalAdrHalfPage,PhysicalAdrAnotherPage; */
	int PageCapacity, PhysicalAdrHigh, PhysicalAdrHalfPage;

	SiSSetMode (HwDeviceExtension, 0x2e);
	data = SiS_GetReg1 (SiS_P3c4, 0x1);
	data = data | 0x20;
	SiS_SetReg1 (SiS_P3c4, 0x01, data);	/* Turn OFF Display  */

	SiS_SetReg1 (SiS_P3c4, 0x13, 0x00);
	SiS_SetReg1 (SiS_P3c4, 0x14, 0xBF);
	buswidth = SiS_ChkBUSWidth_300 (FBAddr);

	MB2Bank = 16;
	Done = 0;
	for (i = 6; i >= 0; i--) {
		if (Done == 1)
			break;
		PseudoRankCapacity = 1 << i;
		for (j = 4; j >= 1; j--) {
			if (Done == 1)
				break;
			PseudoTotalCapacity = PseudoRankCapacity * j;
			PseudoAdrPinCount = 15 - j;
			if (PseudoTotalCapacity <= 64) {
				for (k = 0; k <= 16; k++) {
					if (Done == 1)
						break;
					RankCapacity =
					    buswidth * SiS_DRAMType[k][3];
					AdrPinCount =
					    SiS_DRAMType[k][2] +
					    SiS_DRAMType[k][0];
					if (RankCapacity == PseudoRankCapacity)
						if (AdrPinCount <=
						    PseudoAdrPinCount) {
							if (j == 3) {	/* Rank No */
								BankNumHigh =
								    RankCapacity
								    * MB2Bank *
								    3 - 1;
								BankNumMid =
								    RankCapacity
								    * MB2Bank *
								    1 - 1;
							} else {
								BankNumHigh =
								    RankCapacity
								    * MB2Bank *
								    j - 1;
								BankNumMid =
								    RankCapacity
								    * MB2Bank *
								    j / 2 - 1;
							}
							PageCapacity =
							    (1 <<
							     SiS_DRAMType[k][1])
							    * buswidth * 4;
							PhysicalAdrHigh =
							    BankNumHigh;
							PhysicalAdrHalfPage =
							    (PageCapacity / 2 +
							     PhysicalAdrHigh) %
							    PageCapacity;
							PhysicalAdrOtherPage =
							    PageCapacity *
							    SiS_DRAMType[k][2] +
							    PhysicalAdrHigh;
							/* Write data */
							/*Test */
							temp =
							    (UCHAR)
							    SiS_GetReg1
							    (SiS_P3c4, 0x15);
							SiS_SetReg1 (SiS_P3c4,
								     0x15,
								     (USHORT)
								     (temp &
								      0xFB));

							temp =
							    (UCHAR)
							    SiS_GetReg1
							    (SiS_P3c4, 0x15);
							SiS_SetReg1 (SiS_P3c4,
								     0x15,
								     (USHORT)
								     (temp |
								      0x04));
							/*Test */
							TotalCapacity =
							    SiS_DRAMType[k][3] *
							    buswidth;
							SR13 =
							    SiS_DRAMType[k][4];
							if (buswidth == 4)
								SR14 =
								    (TotalCapacity
								     -
								     1) | 0x80;
							if (buswidth == 2)
								SR14 =
								    (TotalCapacity
								     -
								     1) | 0x40;
							if (buswidth == 1)
								SR14 =
								    (TotalCapacity
								     -
								     1) | 0x00;
							SiS_SetReg1 (SiS_P3c4,
								     0x13,
								     SR13);
							SiS_SetReg1 (SiS_P3c4,
								     0x14,
								     SR14);

							Addr =
							    FBAddr +
							    (BankNumHigh) * 64 *
							    1024 +
							    PhysicalAdrHigh;
							*((USHORT *) (Addr)) =
							    (USHORT)
							    PhysicalAdrHigh;
							Addr =
							    FBAddr +
							    (BankNumMid) * 64 *
							    1024 +
							    PhysicalAdrHigh;
							*((USHORT *) (Addr)) =
							    (USHORT) BankNumMid;
							Addr =
							    FBAddr +
							    (BankNumHigh) * 64 *
							    1024 +
							    PhysicalAdrHalfPage;
							*((USHORT *) (Addr)) =
							    (USHORT)
							    PhysicalAdrHalfPage;
							Addr =
							    FBAddr +
							    (BankNumHigh) * 64 *
							    1024 +
							    PhysicalAdrOtherPage;
							*((USHORT *) (Addr)) =
							    PhysicalAdrOtherPage;

							/* Read data */
							Addr =
							    FBAddr +
							    (BankNumHigh) * 64 *
							    1024 +
							    PhysicalAdrHigh;
							data =
							    *((USHORT *)
							      (Addr));
							if (data ==
							    PhysicalAdrHigh)
								    Done = 1;
						}	/* if struct */
				}	/* for loop (k) */
			}	/* if struct */
		}		/* for loop (j) */
	}			/* for loop (i) */
}

USHORT
SiS_ChkBUSWidth_300 (ULONG FBAddress)
{
	/*USHORT  data; */
	PULONG pVideoMemory;

	pVideoMemory = (PULONG) FBAddress;

	pVideoMemory[0] = 0x01234567L;
	pVideoMemory[1] = 0x456789ABL;
	pVideoMemory[2] = 0x89ABCDEFL;
	pVideoMemory[3] = 0xCDEF0123L;
	if (pVideoMemory[3] == 0xCDEF0123L) {	/*ChannelA128Bit */
		return (4);
	}
	if (pVideoMemory[1] == 0x456789ABL) {	/*ChannelB64Bit */
		return (2);
	}
	return (1);
}
#endif

/* ===============  for 300 dram sizing end    =============== */

/* ============== alan ====================== */
#ifdef CONFIG_FB_SIS_315
UCHAR
SiS_Get310DRAMType (ULONG ROMAddr)
{
	UCHAR data;

	/* 
	   index=SiS_GetReg1(SiS_P3c4,0x1A);
	   index=index&07;
	 */
	if (*pSiS_SoftSetting & SoftDRAMType)
		data = *pSiS_SoftSetting & 0x03;
	else
		data = SiS_GetReg1 (SiS_P3c4, 0x3a) & 0x03;

	return data;
}

void
SiS_Delay15us (ULONG ulMicrsoSec)
{
}

void
SiS_SDR_MRS (void)
{
	USHORT data;

	data = SiS_GetReg1 (SiS_P3c4, 0x16);
	data = data & 0x3F;	/*/ SR16 D7=0,D6=0 */
	SiS_SetReg1 (SiS_P3c4, 0x16, data);	/*/ enable mode register set(MRS) low */
	SiS_Delay15us (0x100);
	data = data | 0x80;	/*/ SR16 D7=1,D6=0 */
	SiS_SetReg1 (SiS_P3c4, 0x16, data);	/*/ enable mode register set(MRS) high */
	SiS_Delay15us (0x100);
}

void
SiS_DDR_MRS (void)
{
	USHORT data;

	/* SR16 <- 1F,DF,2F,AF */

	/* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
	data = SiS_GetReg1 (SiS_P3c4, 0x16);
	data &= 0x0F;
	data |= 0x10;
	SiS_SetReg1 (SiS_P3c4, 0x16, data);

	if (!(SiS_SR15[1][SiS_RAMType] & 0x10)) {
		data &= 0x0F;
	}
	/* SR16 D7=1,D6=1 */
	data |= 0xC0;
	SiS_SetReg1 (SiS_P3c4, 0x16, data);

	/* SR16 D7=1,D6=0,D5=1,D4=0 */
	data &= 0x0F;
	data |= 0x20;
	SiS_SetReg1 (SiS_P3c4, 0x16, data);
	if (!(SiS_SR15[1][SiS_RAMType] & 0x10)) {
		data &= 0x0F;
	}
	/* SR16 D7=1 */
	data |= 0x80;
	SiS_SetReg1 (SiS_P3c4, 0x16, data);
}

void
SiS_SetDRAMModeRegister (ULONG ROMAddr)
{

	if (SiS_Get310DRAMType (ROMAddr) < 2) {
		SiS_SDR_MRS ();
	} else {
		/* SR16 <- 0F,CF,0F,8F */
		SiS_DDR_MRS ();
	}
}

void
SiS_DisableRefresh (void)
{
	USHORT data;

	data = SiS_GetReg1 (SiS_P3c4, 0x17);
	data &= 0xF8;
	SiS_SetReg1 (SiS_P3c4, 0x17, data);

	data = SiS_GetReg1 (SiS_P3c4, 0x19);
	data |= 0x03;
	SiS_SetReg1 (SiS_P3c4, 0x19, data);

}

void
SiS_EnableRefresh (ULONG ROMAddr)
{

	SiS_SetReg1 (SiS_P3c4, 0x17, SiS_SR15[2][SiS_RAMType]);	/* SR17 */

	SiS_SetReg1 (SiS_P3c4, 0x19, SiS_SR15[4][SiS_RAMType]);	/* SR19 */

}

void
SiS_DisableChannelInterleaving (int index, USHORT SiS_DDRDRAM_TYPE[][5])
{
	USHORT data;

	data = SiS_GetReg1 (SiS_P3c4, 0x15);
	data &= 0x1F;
	switch (SiS_DDRDRAM_TYPE[index][3]) {
	case 64:
		data |= 0;
		break;
	case 32:
		data |= 0x20;
		break;
	case 16:
		data |= 0x40;
		break;
	case 4:
		data |= 0x60;
		break;
	}
	SiS_SetReg1 (SiS_P3c4, 0x15, data);

}

void
SiS_SetDRAMSizingType (int index, USHORT DRAMTYPE_TABLE[][5])
{
	USHORT data;

	data = DRAMTYPE_TABLE[index][4];
	SiS_SetReg1 (SiS_P3c4, 0x13, data);

	/* should delay 50 ns */

}

void
SiS_CheckBusWidth_310 (ULONG ROMAddress, ULONG FBAddress)
{
	USHORT data;
	PULONG volatile pVideoMemory;

	pVideoMemory = (PULONG) FBAddress;
	if (SiS_Get310DRAMType (ROMAddress) < 2) {

		SiS_SetReg1 (SiS_P3c4, 0x13, 0x00);
		SiS_SetReg1 (SiS_P3c4, 0x14, 0x12);
		/* should delay */
		SiS_SDR_MRS ();

		SiS_ChannelAB = 0;
		SiS_DataBusWidth = 128;
		pVideoMemory[0] = 0x01234567L;
		pVideoMemory[1] = 0x456789ABL;
		pVideoMemory[2] = 0x89ABCDEFL;
		pVideoMemory[3] = 0xCDEF0123L;
		pVideoMemory[4] = 0x55555555L;
		pVideoMemory[5] = 0x55555555L;
		pVideoMemory[6] = 0xFFFFFFFFL;
		pVideoMemory[7] = 0xFFFFFFFFL;
		if ((pVideoMemory[3] != 0xCDEF0123L)
		    || (pVideoMemory[2] != 0x89ABCDEFL)) {
			/*ChannelA64Bit */
			SiS_DataBusWidth = 64;
			SiS_ChannelAB = 0;
			data = SiS_GetReg1 (SiS_P3c4, 0x14);
			SiS_SetReg1 (SiS_P3c4, 0x14, (USHORT) (data & 0xFD));
		}

		if ((pVideoMemory[1] != 0x456789ABL)
		    || (pVideoMemory[0] != 0x01234567L)) {
			/*ChannelB64Bit */
			SiS_DataBusWidth = 64;
			SiS_ChannelAB = 1;
			data = SiS_GetReg1 (SiS_P3c4, 0x14);