skgeinit.c

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

 *	o Read PCI configuration.
 *	o Change power state to 3.
 *	o Change power state to 0.
 *	o Restore PCI configuration.
 *
 * Returns:
 *	0:	Success.
 *	1:	Power state could not be changed to 3.
 */
static int SkGePciReset(
SK_AC	*pAC,		/* adapter context */
SK_IOC	IoC)		/* IO context */
{
	int		i;
	SK_U16	PmCtlSts;
	SK_U32	Bp1;
	SK_U32	Bp2;
	SK_U16	PciCmd;
	SK_U8	Cls;
	SK_U8	Lat;
	SK_U8	ConfigSpace[PCI_CFG_SIZE];

	/*
	 * Note: Switching to D3 state is like a software reset.
	 *		 Switching from D3 to D0 is a hardware reset.
	 *		 We have to save and restore the configuration space.
	 */
	for (i = 0; i < PCI_CFG_SIZE; i++) {
		SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
	}

	/* We know the RAM Interface Arbiter is enabled. */
	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
	if ((PmCtlSts & PCI_PM_STATE) != PCI_PM_STATE_D3) {
		return (1);
	}

	/*
	 * Return to D0 state.
	 */
	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);

	/* Check for D0 state. */
	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
	if ((PmCtlSts & PCI_PM_STATE) != PCI_PM_STATE_D0) {
		return (1);
	}

	/*
	 * Check PCI Config Registers.
	 */
	SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
	SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
	SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
	SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
	SkPciReadCfgByte(pAC, PCI_LAT_TIM, &lat);
	if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
		Lat != 0 ) {
		return (0);
	}

	/*
	 * Restore Config Space.
	 */
	for (i = 0; i < PCI_CFG_SIZE; i++) {
		SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
	}

	return (0);
}	/* SkGePciReset */

#endif	/* SK_PCI_RESET */

/******************************************************************************
 *
 *	SkGeInit1() - Level 1 Initialization
 *
 * Description:
 *	o Do a software reset.
 *	o Clear all reset bits.
 *	o Verify that the detected hardware is present.
 *	  Return an error if not.
 *	o Get the hardware configuration
 *		+ Read the number of MACs/Ports.
 *		+ Read the RAM size.
 *		+ Read the PCI Revision ID.
 *		+ Find out the adapters host clock speed
 *		+ Read and check the PHY type
 *
 * Returns:
 *	0:	success
 *	5:	Unexpected PHY type detected
 */
static int SkGeInit1(
SK_AC	*pAC,		/* adapter context */
SK_IOC	IoC)		/* IO context */
{
	SK_U8	Byte;
	SK_U16	Word;
	int	RetVal;
	int	i;

	RetVal = 0;

#ifdef SK_PCI_RESET
	(void)SkGePciReset(pAC, IoC);
#endif	/* SK_PCI_RESET */

	/* Do the reset */
	SK_OUT8(IoC, B0_CTST, CS_RST_SET);

	/* Release the reset */
	SK_OUT8(IoC, B0_CTST, CS_RST_CLR);

	/* Reset all error bits in the PCI STATUS register */
	/*
	 * Note: Cfg cycles cannot be used, because they are not
	 *		 available on some platforms after 'boot time'.
	 */
	SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
	SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
	SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
	SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

	/* Release Master_Reset */
	SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);

	/* Read number of MACs */
	SK_IN8(IoC, B2_MAC_CFG, &Byte);
	if (Byte & CFG_SNG_MAC) {
		pAC->GIni.GIMacsFound = 1;
	}
	else {
		pAC->GIni.GIMacsFound = 2;
	}
	SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
	pAC->GIni.GIPciHwRev = (int) Byte;

	/* Read the adapters RAM size */
	SK_IN8(IoC, B2_E_0, &Byte);
	if (Byte == 3) {
		pAC->GIni.GIRamSize = (int)(Byte-1) * 512;
		pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
	}
	else {
		pAC->GIni.GIRamSize = (int)Byte * 512;
		pAC->GIni.GIRamOffs = 0;
	}

	/* All known GE Adapters works with 53.125 MHz host clock */
	pAC->GIni.GIHstClkFact = SK_FACT_53;
	pAC->GIni.GIPollTimerVal =
		SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
	
	/* Read the PHY type */
	SK_IN8(IoC, B2_E_1, &Byte);
	Byte &= 0x0f;	/* the PHY type is stored in the lower nibble */
	for (i=0; i<pAC->GIni.GIMacsFound; i++) {
		pAC->GIni.GP[i].PhyType = Byte;
		switch (Byte) {
		case SK_PHY_XMAC:
			pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
			break;
		case SK_PHY_BCOM:
			pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
			break;
		case SK_PHY_LONE:
			pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
			break;
		case SK_PHY_NAT:
			pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
			break;
		default:
			/* ERROR: unexpected PHY typ detected */
			RetVal = 5;
			break;
		}
	}
	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
		("PHY type: %d  PHY addr: %x\n", pAC->GIni.GP[i].PhyType,
		pAC->GIni.GP[i].PhyAddr));

	return (RetVal);
}	/* SkGeInit1*/


/******************************************************************************
 *
 *	SkGeInit2() - Level 2 Initialization
 *
 * Description:
 *	- start the Blink Source Counter
 *	- start the Descriptor Poll Timer
 *	- configure the MAC-Arbiter
 *	- configure the Packet-Arbiter
 *	- enable the Tx Arbiters
 *	- enable the RAM Interface Arbiter
 *
 * Returns:
 *	nothing
 */
static void SkGeInit2(
SK_AC	*pAC,		/* adapter context */
SK_IOC	IoC)		/* IO context */
{
	SK_GEPORT *pPrt;
	SK_U32	DWord;
	int	i;

	/* start the Blink Source Counter */
	DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
	SK_OUT32(IoC, B2_BSC_INI, DWord);
	SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);

	/* start the Descriptor Poll Timer */
	if (pAC->GIni.GIPollTimerVal != 0) {
		if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
			pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;

			/* Create an Error Log Entry */
			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
		}
		SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
		SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
	}

	/*
	 * Configure
	 *	- the MAC-Arbiter and
	 *	- the Paket Arbiter
	 *
	 * The MAC and the packet arbiter will be started once
	 * and never be stopped.
	 */
	SkGeInitMacArb(pAC, IoC);
	SkGeInitPktArb(pAC, IoC);

	/* enable the Tx Arbiters */
	SK_OUT8(IoC, MR_ADDR(MAC_1, TXA_CTRL), TXA_ENA_ARB);
	if (pAC->GIni.GIMacsFound > 1) {
		SK_OUT8(IoC, MR_ADDR(MAC_2, TXA_CTRL), TXA_ENA_ARB);
	}

	/* enable the RAM Interface Arbiter */
	SkGeInitRamIface(pAC, IoC);

	for (i = 0; i < SK_MAX_MACS; i++) {
		pPrt = &pAC->GIni.GP[i];
		if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
			pPrt->PRxCmd |= XM_RX_BIG_PK_OK;
		}

		if (pPrt->PLinkModeConf == SK_LMODE_HALF) {
			/*
			 * If in manual half duplex mode
			 * the other side might be in full duplex mode
			 * so ignore if a carrier extension is not seen on
			 * frames received
			 */
			pPrt->PRxCmd |= XM_RX_DIS_CEXT;
		}

	}
}	/* SkGeInit2 */

/******************************************************************************
 *
 *	SkGeInit() - Initialize the GE Adapter with the specified level.
 *
 * Description:
 *	Level	0:	Initialize the Module structures.
 *	Level	1:	Generic Hardware Initialization. The
 *			IOP/MemBase pointer has to be set before
 *			calling this level.
 *
 *			o Do a software reset.
 *			o Clear all reset bits.
 *			o Verify that the detected hardware is present.
 *			  Return an error if not.
 *			o Get the hardware configuration
 *				+ Set GIMacsFound with the number of MACs.
 *				+ Store the RAM size in GIRamSize.
 *				+ Save the PCI Revision ID in GIPciHwRev.
 *			o return an error
 *				if Number of MACs > SK_MAX_MACS
 *
 *			After returning from Level 0 the adapter
 *			may be accessed with IO operations.
 *
 *	Level	2:	start the Blink Source Counter
 *
 * Returns:
 *	0:	success
 *	1:	Number of MACs exceeds SK_MAX_MACS	( after level 1)
 *	2:	Adapter not present or not accessable
 *	3:	Illegal initialization level
 *	4:	Initialization Level 1 Call missing
 *	5:	Unexpected PHY type detected
 */
int	SkGeInit(
SK_AC	*pAC,		/* adapter context */
SK_IOC	IoC,		/* IO context */
int		Level)		/* initialization level */
{
	int	RetVal;		/* return value */
	SK_U32	DWord;

	RetVal = 0;
	SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
		("SkGeInit(Level %d)\n", Level));

	switch (Level) {
	case SK_INIT_DATA:
		/* Initialization Level 0 */
		SkGeInit0(pAC, IoC);
		pAC->GIni.GILevel = SK_INIT_DATA;
		break;
	case SK_INIT_IO:
		/* Initialization Level 1 */
		RetVal = SkGeInit1(pAC, IoC);

		/* Check if the adapter seems to be accessable */
		SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);
		SK_IN32(IoC, B2_IRQM_INI, &DWord);
		SK_OUT32(IoC, B2_IRQM_INI, 0x00000000L);
		if (DWord != 0x11335577L) {
			RetVal = 2;
			break;
		}

		/* Check if the number of GIMacsFound matches SK_MAX_MACS */
		if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
			RetVal = 1;
			break;
		}

		/* Level 1 successfully passed */
		pAC->GIni.GILevel = SK_INIT_IO;
		break;
	case SK_INIT_RUN:
		/* Initialization Level 2 */
		if (pAC->GIni.GILevel != SK_INIT_IO) {
#ifndef	SK_DIAG
			SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG);
#endif
			RetVal = 4;
			break;
		}
		SkGeInit2(pAC, IoC);

		/* Level 2 successfully passed */
		pAC->GIni.GILevel = SK_INIT_RUN;
		break;
	default:
		/* Create an Error Log Entry */
		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
		RetVal = 3;
		break;
	}

	return (RetVal);
}	/* SkGeInit*/


/******************************************************************************
 *
 *	SkGeDeInit() - Deinitialize the adapter.
 *
 * Description:
 *	All ports of the adapter will be stopped if not already done.
 *	Do a software reset and switch off all LEDs.
 *
 * Returns:
 *	nothing
 */
void	SkGeDeInit(
SK_AC	*pAC,		/* adapter context */
SK_IOC	IoC)		/* IO context */
{
	int	i;
	SK_U16	Word;

	/* Ensure I2C is ready. */
	SkI2cWaitIrq(pAC, IoC);

	/* Stop all current transfer activity */
	for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
		if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
			pAC->GIni.GP[i].PState != SK_PRT_RESET) {

			SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
		}
	}

	/* Reset all bits in the PCI STATUS register */
	/*
	 * Note: Cfg cycles cannot be used, because they are not
	 *	 available on some platforms after 'boot time'.
	 */
	SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
	SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
	SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
	SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

	/* Do the reset, all LEDs are switched off now */
	SK_OUT8(IoC, B0_CTST, CS_RST_SET);
}	/* SkGeDeInit*/


/******************************************************************************
 *
 *	SkGeInitPort()	Initialize the specified prot.
 *
 * Description:
 *	PRxQSize, PXSQSize, and PXAQSize has to be
 *	configured for the specified port before calling this
 *	function. The descriptor rings has to be initialized, too.
 *
 *	o (Re)configure queues of the specified port.
 *	o configure the XMAC of the specified port.
 *	o put ASIC and XMAC(s) in operational mode.
 *	o initialize Rx/Tx and Sync LED
 *	o initialize RAM Buffers and MAC FIFOs
 *
 *	The port is ready to connect when returning.
 *
 * Note:
 *	The XMACs Rx and Tx state machine is still disabled when
 *	returning.
 *
 * Returns:
 *	0:	success
 *	1:	Queue size initialization error. The configured values
 *		for PRxQSize, PXSQSize, or PXAQSize are invalid for one
 *		or more queues. The specified port was NOT initialized.
 *		An error log entry was generated.
 *	2:	The port has to be stopped before it can be initialized again.
 */
int SkGeInitPort(
SK_AC	*pAC,		/* adapter context */
SK_IOC	IoC,		/* IO context */
int		Port)		/* Port to configure */
{
	SK_GEPORT *pPrt;

	pPrt = &pAC->GIni.GP[Port];

	if (SkGeCheckQSize(pAC, Port) != 0) {
		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
		return (1);
	}
	if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
		SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
		return (2);
	}

	/* Configuration ok, initialize the Port now */

	/* Initialize Rx, Tx and Link LED */
	/*
	 * If 1000BT Phy needs LED initialization than swap
	 * LED and XMAC initialization order
	 */
 	SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
 	SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
	/* The Link LED is initialized by RLMT or Diagnostics itself */ 

	/* Do NOT initialize the Link Sync Counter */

	/*
	 * Configure
	 *	- XMAC
	 *	- MAC FIFOs
	 *	- RAM Buffers
	 *	- enable Force Sync bit if synchronous queue available
	 *	- BMUs
	 */
	SkXmInitMac(pAC, IoC, Port);
	SkGeInitMacFifo(pAC, IoC, Port);
	SkGeInitRamBufs(pAC, IoC, Port);
	if (pPrt->PXSQSize != 0) {
		SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
	}
	SkGeInitBmu(pAC, IoC, Port);

	/* Mark port as initialized. */
	pPrt->PState = SK_PRT_INIT;
	pAC->GIni.GIAnyPortAct = SK_TRUE;

	return (0);
}	/* SkGeInitPort */