skgehw.h

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

/******************************************************************************
 *
 * Name:	skgehw.h
 * Project:	GEnesis, PCI Gigabit Ethernet Adapter
 * Version:	$Revision: 1.36 $
 * Date:	$Date: 2000/11/09 12:32:49 $
 * Purpose:	Defines and Macros for the Gigabit Ethernet Adapter Product
 *		Family
 *
 ******************************************************************************/

/******************************************************************************
 *
 *	(C)Copyright 1998-2000 SysKonnect GmbH.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

/******************************************************************************
 *
 * History:
 * $Log: skgehw.h,v $
 * Revision 1.36  2000/11/09 12:32:49  rassmann
 * Renamed variables.
 *
 * Revision 1.35  2000/05/19 10:17:13  cgoos
 * Added inactivity check in PHY_READ (in DEBUG mode only).
 *
 * Revision 1.34  1999/11/22 13:53:40  cgoos
 * Changed license header to GPL.
 *
 * Revision 1.33  1999/08/27 11:17:10  malthoff
 * It's more savely to put bracket around marco parameters.
 * Brackets added for PHY_READ and PHY_WRITE.
 *
 * Revision 1.32  1999/05/19 07:31:01  cgoos
 * Changes for 1000Base-T.
 * Added HWAC_LINK_LED macro.
 *
 * Revision 1.31  1999/03/12 13:27:40  malthoff
 * Remove __STDC__.
 *
 * Revision 1.30  1999/02/09 09:28:20  malthoff
 * Add PCI_ERRBITS.
 *
 * Revision 1.29  1999/01/26 08:55:48  malthoff
 * Bugfix: The 16 bit field releations inside the descriptor are
 * 	endianess dependend if the descriptor reversal feature
 * 	(PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
 * 	Drivers which use this feature has to set the define
 * 	SK_USE_REV_DESC.
 *
 * Revision 1.28  1998/12/10 11:10:22  malthoff
 * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted.
 *
 * Revision 1.27  1998/11/13 14:19:21  malthoff
 * Bug Fix: The bit definition of B3_PA_CTRL has completely
 * changed from HW Spec v1.3 to v1.5.
 *
 * Revision 1.26  1998/11/04 08:31:48  cgoos
 * Fixed byte ordering in XM_OUTADDR/XM_OUTHASH macros.
 *
 * Revision 1.25  1998/11/04 07:16:25  cgoos
 * Changed byte ordering in XM_INADDR/XM_INHASH again.
 *
 * Revision 1.24  1998/11/02 11:08:43  malthoff
 * RxCtrl and TxCtrl must be volatile.
 *
 * Revision 1.23  1998/10/28 13:50:45  malthoff
 * Fix: Endian support missing in XM_IN/OUT-ADDR/HASH macros.
 *
 * Revision 1.22  1998/10/26 08:01:36  malthoff
 * RX_MFF_CTRL1 is split up into RX_MFF_CTRL1,
 * RX_MFF_STAT_TO, and RX_MFF_TIST_TO.
 * TX_MFF_CTRL1 is split up TX_MFF_CTRL1 and TX_MFF_WAF.
 *
 * Revision 1.21  1998/10/20 07:43:10  malthoff
 * Fix: XM_IN/OUT/ADDR/HASH macros:
 * The pointer must be casted.
 *
 * Revision 1.20  1998/10/19 15:53:59  malthoff
 * Remove ML proto definitions.
 *
 * Revision 1.19  1998/10/16 14:40:17  gklug
 * fix: typo B0_XM_IMSK regs
 *
 * Revision 1.18  1998/10/16 09:46:54  malthoff
 * Remove temp defines for ML diag prototyp.
 * Fix register definition for B0_XM1_PHY_DATA, B0_XM1_PHY_DATA
 * B0_XM2_PHY_DATA, B0_XM2_PHY_ADDR, B0_XA1_CSR, B0_XS1_CSR,
 * B0_XS2_CSR, and B0_XA2_CSR.
 *
 * Revision 1.17  1998/10/14 06:03:14  cgoos
 * Changed shifted constant to ULONG.
 *
 * Revision 1.16  1998/10/09 07:05:41  malthoff
 * Rename ALL_PA_ENA_TO to PA_ENA_TO_ALL.
 *
 * Revision 1.15  1998/10/05 07:54:23  malthoff
 * Split up RB_CTRL and it's bit definition into
 * RB_CTRL, RB_TST1, and RB_TST2.
 * Rename RB_RX_HTPP to RB_RX_LTPP.
 * Add ALL_PA_ENA_TO. Modify F_WATER_MARK
 * according to HW Spec. v1.5.
 * Add MFF_TX_CTRL_DEF.
 *
 * Revision 1.14  1998/09/28 13:31:16  malthoff
 * bug fix: B2_MAC_3 is 0x110 not 0x114
 *
 * Revision 1.13  1998/09/24 14:42:56  malthoff
 * Split the RX_MFF_TST into RX_MFF_CTRL2,
 * RX_MFF_TST1, and RX_MFF_TST2.
 * Rename RX_MFF_CTRL to RX_MFF_CTRL1.
 * Add BMU bit CSR_SV_IDLE.
 * Add macros PHY_READ() and PHY_WRITE().
 * Rename macro SK_ADDR() to SK_HW_ADDR()
 * because of conflicts with the Address Module.
 *
 * Revision 1.12  1998/09/16 07:25:33  malthoff
 * Change the parameter order in the XM_INxx and XM_OUTxx macros,
 * to have the IoC as first parameter.
 *
 * Revision 1.11  1998/09/03 09:58:41  malthoff
 * Rework the XM_xxx macros. Use {} instead of () to
 * be compatible with SK_xxx macros which are defined
 * with {}.
 *
 * Revision 1.10  1998/09/02 11:16:39  malthoff
 * Temporary modify B2_I2C_SW to make tests with
 * the GE/ML prototyp.
 *
 * Revision 1.9  1998/08/19 09:11:49  gklug
 * fix: struct are removed from c-source (see CCC)
 * add: typedefs for all structs
 *
 * Revision 1.8  1998/08/18 08:27:27  malthoff
 * Add some temporary workarounds to test GE
 * sources with the ML.
 *
 * Revision 1.7  1998/07/03 14:42:26  malthoff
 * bug fix: Correct macro XMA().
 * Add temporary workaround to access the PCI config space over IO
 *
 * Revision 1.6  1998/06/23 11:30:36  malthoff
 * Remove ';' with ',' in macors.
 *
 * Revision 1.5  1998/06/22 14:20:57  malthoff
 * Add macro SK_ADDR(Base,Addr).
 *
 * Revision 1.4  1998/06/19 13:35:43  malthoff
 * change 'pGec' with 'pAC'
 *
 * Revision 1.3  1998/06/17 14:58:16  cvs
 * Lost keywords reinserted.
 *
 * Revision 1.1  1998/06/17 14:16:36  cvs
 * created
 *
 *
 ******************************************************************************/

#ifndef __INC_SKGEHW_H
#define __INC_SKGEHW_H

#ifdef __cplusplus
extern "C" {
#endif	/* __cplusplus */

/* defines ********************************************************************/

/*
 * Configuration Space header
 * Since this module is used for different OS', those may be
 * duplicate on some of them (e.g. Linux). But to keep the
 * common source, we have to live with this...
 */
#define	PCI_VENDOR_ID	0x00	/* 16 bit	Vendor ID */
#define	PCI_DEVICE_ID	0x02	/* 16 bit	Device ID */
#define	PCI_COMMAND		0x04	/* 16 bit	Command */
#define	PCI_STATUS		0x06	/* 16 bit	Status */
#define	PCI_REV_ID		0x08	/*  8 bit	Revision ID */
#define	PCI_CLASS_CODE	0x09	/* 24 bit	Class Code */
#define	PCI_CACHE_LSZ	0x0c	/*  8 bit	Cache Line Size */
#define	PCI_LAT_TIM		0x0d	/*  8 bit	Latency Timer */
#define	PCI_HEADER_T	0x0e	/*  8 bit	Header Type */
#define	PCI_BIST		0x0f	/*  8 bit	Built-in selftest */
#define	PCI_BASE_1ST	0x10	/* 32 bit	1st Base address */
#define	PCI_BASE_2ND	0x14	/* 32 bit	2nd Base address */
	/* Byte 18..2b:	reserved */
#define	PCI_SUB_VID		0x2c	/* 16 bit	Subsystem Vendor ID */
#define	PCI_SUB_ID		0x2e	/* 16 bit	Subsystem ID */
#define	PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */
	/* Byte 34..33:	reserved */
#define PCI_CAP_PTR		0x34	/*  8 bit 	Capabilities Ptr */
	/* Byte 35..3b:	reserved */
#define	PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */
#define	PCI_IRQ_PIN		0x3d	/*  8 bit	Interrupt Pin */
#define	PCI_MIN_GNT		0x3e	/*  8 bit	Min_Gnt */
#define	PCI_MAX_LAT		0x3f	/*  8 bit	Max_Lat */
	/* Device Dependent Region */
#define	PCI_OUR_REG_1	0x40	/* 32 bit 	Our Register 1 */
#define	PCI_OUR_REG_2	0x44	/* 32 bit 	Our Register 2 */
	/* Power Management Region */
#define PCI_PM_CAP_ID	0x48	/*  8 bit 	Power Management Cap. ID */
#define PCI_PM_NITEM	0x49	/*  8 bit 	Next Item Ptr */
#define PCI_PM_CAP_REG	0x4a	/* 16 bit 	Power Management Capabilities */
#define PCI_PM_CTL_STS	0x4c	/* 16 bit 	Power Manag. Control/Status */
	/* Byte 0x4e:	reserved */
#define PCI_PM_DAT_REG	0x4f	/*  8 bit 	Power Manag. Data Register */
	/* VPD Region */
#define	PCI_VPD_CAP_ID	0x50	/*  8 bit 	VPD Cap. ID */
#define PCI_VPD_NITEM	0x51	/*  8 bit 	Next Item Ptr */
#define PCI_VPD_ADR_REG	0x52	/* 16 bit 	VPD Address Register */
#define PCI_VPD_DAT_REG	0x54	/* 32 bit 	VPD Data Register */
	/* Byte 58..ff:	reserved */

/*
 * I2C Address (PCI Config)
 *
 * Note: The temperature and voltage sensors are relocated on a different
 *	 I2C bus.
 */
#define I2C_ADDR_VPD	0xA0	/* I2C address for the VPD EEPROM */

/*
 * Define Bits and Values of the registers
 */
/*	PCI_VENDOR_ID	16 bit	Vendor ID */
/*	PCI_DEVICE_ID	16 bit	Device ID */
/* Values for Vendor ID and Device ID shall be patched into the code */
/*	PCI_COMMAND	16 bit	Command */
								/* Bit 15..10:	reserved */
#define	PCI_FBTEN		(1<<9)	/* Bit 9:	Fast Back-To-Back enable */
#define	PCI_SERREN		(1<<8)	/* Bit 8:	SERR enable */
#define	PCI_ADSTEP		(1<<7)	/* Bit 7:	Address Stepping */
#define	PCI_PERREN		(1<<6)	/* Bit 6:	Parity Report Response enable */
#define	PCI_VGA_SNOOP	(1<<5)	/* Bit 5:	VGA palette snoop */
#define	PCI_MWIEN		(1<<4)	/* Bit 4:	Memory write an inv cycl ena */
#define	PCI_SCYCEN		(1<<3)	/* Bit 3:	Special Cycle enable */
#define	PCI_BMEN		(1<<2)	/* Bit 2:	Bus Master enable */
#define	PCI_MEMEN		(1<<1)	/* Bit 1:	Memory Space Access enable */
#define	PCI_IOEN		(1<<0)	/* Bit 0:	IO Space Access enable */

/*	PCI_STATUS	16 bit	Status */
#define	PCI_PERR		(1<<15)	/* Bit 15:	Parity Error */
#define	PCI_SERR		(1<<14)	/* Bit 14:	Signaled SERR */
#define	PCI_RMABORT		(1<<13)	/* Bit 13:	Received Master Abort */
#define	PCI_RTABORT		(1<<12)	/* Bit 12:	Received Target Abort */
								/* Bit 11:	reserved */
#define	PCI_DEVSEL		(3<<9)	/* Bit 10..9:	DEVSEL Timing */
#define	PCI_DEV_FAST	(0<<9)	/*		fast */
#define	PCI_DEV_MEDIUM	(1<<9)	/*		medium */
#define	PCI_DEV_SLOW	(2<<9)	/*		slow */
#define	PCI_DATAPERR	(1<<8)	/* Bit 8:	DATA Parity error detected */
#define	PCI_FB2BCAP		(1<<7)	/* Bit 7:	Fast Back-to-Back Capability */
#define	PCI_UDF			(1<<6)	/* Bit 6:	User Defined Features */
#define PCI_66MHZCAP	(1<<5)	/* Bit 5:	66 MHz PCI bus clock capable */
#define PCI_NEWCAP		(1<<4)	/* Bit 4:	New cap. list implemented */
								/* Bit 3..0:	reserved */

#define PCI_ERRBITS	(PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\
			PCI_DATAPERR)

/*	PCI_CLASS_CODE	24 bit	Class Code */
/*	Byte 2:		Base Class		(02) */
/*	Byte 1:		SubClass		(00) */
/*	Byte 0:		Programming Interface	(00) */

/*	PCI_CACHE_LSZ	8 bit	Cache Line Size */
/*	Possible values: 0,2,4,8,16,32,64,128	*/

/*	PCI_HEADER_T	8 bit	Header Type */
#define	PCI_HD_MF_DEV	(1<<7)	/* Bit 7:	0= single, 1= multi-func dev */
#define	PCI_HD_TYPE		0x7f	/* Bit 6..0:	Header Layout 0= normal */

/*	PCI_BIST	8 bit	Built-in selftest */
/*	Built-in Self test not supported (optional) */

/*	PCI_BASE_1ST	32 bit	1st Base address */
#define	PCI_MEMSIZE		0x4000L		/* use 16 kB Memory Base */
#define	PCI_MEMBASE_MSK 0xffffc000L	/* Bit 31..14:	Memory Base Address */
#define	PCI_MEMSIZE_MSK 0x00003ff0L	/* Bit 13.. 4:	Memory Size Req. */
#define	PCI_PREFEN		(1L<<3)		/* Bit	3:	Prefetchable */
#define	PCI_MEM_TYP		(3L<<2)		/* Bit	2.. 1:	Memory Type */
#define	PCI_MEM32BIT	(0L<<1)		/* Base addr anywhere in 32 Bit range */
#define	PCI_MEM1M		(1L<<1)		/* Base addr below 1 MegaByte */