xmac_ii.h

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

/******************************************************************************
 *
 * Name:	xmac_ii.h
 * Project:	GEnesis, PCI Gigabit Ethernet Adapter
 * Version:	$Revision: 1.28 $
 * Date:	$Date: 2000/11/09 12:32:49 $
 * Purpose:	Defines and Macros for XaQti's Gigabit Ethernet Controller
 *
 ******************************************************************************/

/******************************************************************************
 *
 *	(C)Copyright 1998-2000 SysKonnect GmbH.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

/******************************************************************************
 *
 * History:
 *
 *	$Log: xmac_ii.h,v $
 *	Revision 1.28  2000/11/09 12:32:49  rassmann
 *	Renamed variables.
 *	
 *	Revision 1.27  2000/05/17 11:00:46  malthoff
 *	Add bit for enable/disable power management in BCOM chip.
 *	
 *	Revision 1.26  1999/11/22 14:03:00  cgoos
 *	Changed license header to GPL.
 *	
 *	Revision 1.25  1999/08/12 19:19:38  malthoff
 *	Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet.
 *	
 *	Revision 1.24  1999/07/30 11:27:21  cgoos
 *	Fixed a missing end-of-comment.
 *	
 *	Revision 1.23  1999/07/30 07:03:31  malthoff
 *	Cut some long comments.
 *	Correct the XMAC PHY ID definitions.
 *	
 *	Revision 1.22  1999/05/19 07:33:18  cgoos
 *	Changes for 1000Base-T.
 *	
 *	Revision 1.21  1999/03/25 07:46:11  malthoff
 *	Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers.
 *	
 *	Revision 1.20  1999/03/12 13:36:09  malthoff
 *	Remove __STDC__.
 *
 *	Revision 1.19  1998/12/10 12:22:54  gklug
 *	fix: RX_PAGE must be in interrupt mask
 *
 *	Revision 1.18  1998/12/10 10:36:36  gklug
 *	fix: swap of pause bits
 *
 *	Revision 1.17  1998/11/18 13:21:45  gklug
 *	fix: Default interrupt mask
 *
 *	Revision 1.16  1998/10/29 15:53:21  gklug
 *	fix: Default mask uses ASS (GP0) signal
 *
 *	Revision 1.15  1998/10/28 13:52:52  malthoff
 *	Add new bits in RX_CMD register.
 *
 *	Revision 1.14  1998/10/19 15:34:53  gklug
 *	fix: typos
 *
 *	Revision 1.13  1998/10/14 07:19:03  malthoff
 *	bug fix: Every define which describes bit 31
 *	must be declared as unsigned long 'UL'.
 *	fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE.
 *	Remove ANP defines. Rework the RFB defines.
 *
 *	Revision 1.12  1998/10/14 06:22:44  cgoos
 *	Changed shifted constant to ULONG.
 *
 *	Revision 1.11  1998/10/14 05:43:26  gklug
 *	add: shift pause codeing
 *	fix: PAUSE bits definition
 *
 *	Revision 1.10  1998/10/13 09:19:21  malthoff
 *	Again change XMR_FS_ANY_ERR because of new info from XaQti.
 *
 *	Revision 1.9  1998/10/09 07:58:30  malthoff
 *	Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR.
 *
 *	Revision 1.8  1998/10/09 07:18:17  malthoff
 *	bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE
 *	are not inverted! Bug XM_DEF_MSK is inverted.
 *
 *	Revision 1.7  1998/10/05 08:04:32  malthoff
 *	bug fix: XM_PAUSE_MODE and XM_DEF_MODE
 *	must be inverted declarations.
 *
 *	Revision 1.6  1998/09/28 13:38:18  malthoff
 *	Add default modes and masks XM_DEF_MSK,
 *	XM_PAUSE_MODE and XM_DEF_MODE
 *
 *	Revision 1.5  1998/09/16 14:42:04  malthoff
 *	Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register.
 *
 *	Revision 1.4  1998/08/20 14:59:47  malthoff
 *	Rework this file after reading the XaQti data sheet
 *	"Differences between Rev. B2 & Rev. C XMAC II".
 *	This file is now 100% XMAC II Rev. C complained.
 *
 *	Revision 1.3  1998/06/29 12:18:23  malthoff
 *	Correct XMR_FS_ANY_ERR definition.
 *
 *	Revision 1.2  1998/06/29 12:10:56  malthoff
 *	Add define XMR_FS_ANY_ERR.
 *
 *	Revision 1.1  1998/06/19 13:37:17  malthoff
 *	created.
 *
 *
 ******************************************************************************/

#ifndef __INC_XMAC_H
#define __INC_XMAC_H

#ifdef __cplusplus
extern "C" {
#endif	/* __cplusplus */

/* defines ********************************************************************/

/*
 * XMAC II registers
 *
 * The XMAC registers are 16 or 32 bits wide. The XMACs host processor
 * interface is set to 16 bit mode, therefore ALL registers will be
 * addressed with 16 bit accesses.
 *
 * The following macros are provided to access the XMAC registers
 * XM_IN16(), XM_OUT16, XM_IN32(), MX_OUT32(), XM_INADR(), XM_OUTADR(),
 * XM_INHASH(), and XM_OUTHASH().
 * The macros are defined in SkGeHw.h.
 *
 * Note:	NA reg	= Network Address e.g DA, SA etc.
 *
 */
#define XM_MMU_CMD	0x0000		/* 16 bit r/w	MMU Command Register */
	/* 0x0004:		reserved */
#define XM_POFF		0x0008		/* 32 bit r/w	Packet Offset Register */
#define XM_BURST	0x000c		/* 32 bit r/w	Burst Register for half duplex*/
#define XM_1L_VLAN_TAG	0x0010	/* 16 bit r/w	One Level VLAN Tag ID */
#define XM_2L_VLAN_TAG	0x0014	/* 16 bit r/w	Two Level VLAN Tag ID */
	/* 0x0018 - 0x001e:	reserved */
#define XM_TX_CMD	0x0020		/* 16 bit r/w	Transmit Command Register */
#define	XM_TX_RT_LIM	0x0024	/* 16 bit r/w	Transmit Retry Limit Register */
#define XM_TX_STIME	0x0028		/* 16 bit r/w	Transmit Slottime Register */
#define XM_TX_IPG	0x002c		/* 16 bit r/w	Transmit Inter Packet Gap */
#define XM_RX_CMD	0x0030		/* 16 bit r/w	Receive Command Register */
#define XM_PHY_ADDR	0x0034		/* 16 bit r/w	PHY Address Register */
#define	XM_PHY_DATA	0x0038		/* 16 bit r/w	PHY Data Register */
	/* 0x003c: 		reserved */
#define XM_GP_PORT	0x0040		/* 32 bit r/w	General Purpose Port Register */
#define XM_IMSK		0x0044		/* 16 bit r/w	Interrupt Mask Register */
#define XM_ISRC		0x0048		/* 16 bit ro	Interrupt Status Register */
#define XM_HW_CFG	0x004c		/* 16 bit r/w	Hardware Config Register */
	/* 0x0050 - 0x005e:	reserved */
#define XM_TX_LO_WM	0x0060		/* 16 bit r/w	Tx FIFO Low Water Mark */
#define XM_TX_HI_WM	0x0062		/* 16 bit r/w	Tx FIFO High Water Mark */
#define XM_TX_THR	0x0064		/* 16 bit r/w	Tx Request Threshold */
#define	XM_HT_THR	0x0066		/* 16 bit r/w	Host Request Threshold */
#define	XM_PAUSE_DA	0x0068		/* NA reg r/w	Pause Destination Address */
	/* 0x006e: 		reserved */
#define XM_CTL_PARA	0x0070		/* 32 bit r/w	Control Parameter Register */
#define XM_MAC_OPCODE	0x0074	/* 16 bit r/w	Opcode for MAC control frames */
#define XM_MAC_PTIME	0x0076	/* 16 bit r/w	Pause time for MAC ctrl frames*/
#define XM_TX_STAT	0x0078		/* 32 bit ro	Tx Status LIFO Register */

	/* 0x0080 - 0x00fc:	16 NA reg r/w	Exakt Match Address Registers */
	/* 				use the XM_EMX() macro to address */
#define XM_EXM_START	0x0080	/* r/w	Start Address of the EXM Regs */

	/*
	 * XM_EXM(Reg)
	 *
	 * returns the XMAC address offset off specified Exakt Match Addr Reg
	 *
	 * para:	Reg	EXM register to addr	(0 .. 15)
	 *
	 * usage:	XM_INADDR(XMAC_1,pAC,XM_EXM(i),&val[i]) ;
	 */
#define XM_EXM(Reg)	(XM_EXM_START + ((Reg) << 3))

#define XM_SRC_CHK		0x0100	/* NA reg r/w	Source Check Address Register */
#define XM_SA			0x0108	/* NA reg r/w	Station Address Register */
#define XM_HSM			0x0110	/* 64 bit r/w	Hash Match Address Registers */
#define XM_RX_LO_WM		0x0118	/* 16 bit r/w	Receive Low Water Mark */
#define XM_RX_HI_WM		0x011a	/* 16 bit r/w	Receive High Water Mark */
#define XM_RX_THR		0x011c	/* 32 bit r/w	Receive Request Threshold */
#define XM_DEV_ID		0x0120	/* 32 bit ro	Device ID Register */
#define XM_MODE			0x0124	/* 32 bit r/w	Mode Register */
#define XM_LSA			0x0128	/* NA reg ro	Last Source Register */
	/* 0x012e:		reserved */
#define XM_TS_READ		0x0130	/* 32 bit ro	TimeStamp Read Regeister */
#define XM_TS_LOAD		0x0134	/* 32 bit ro	TimeStamp Load Value */
	/* 0x0138 - 0x01fe:	reserved */
#define XM_STAT_CMD	0x0200	/* 16 bit r/w	Statistics Command Register */
#define	XM_RX_CNT_EV	0x0204	/* 32 bit ro	Rx Counter Event Register */
#define XM_TX_CNT_EV	0x0208	/* 32 bit ro	Tx Counter Event Register */
#define XM_RX_EV_MSK	0x020c	/* 32 bit r/w	Rx Counter Event Mask */
#define XM_TX_EV_MSK	0x0210	/* 32 bit r/w	Tx Counter Event Mask */
	/* 0x0204 - 0x027e:	reserved */
#define XM_TXF_OK		0x0280	/* 32 bit ro	Frames Transmitted OK Conuter */
#define XM_TXO_OK_HI	0x0284	/* 32 bit ro	Octets Transmitted OK High Cnt*/
#define XM_TXO_OK_LO	0x0288	/* 32 bit ro	Octets Transmitted OK Low Cnt */
#define XM_TXF_BC_OK	0x028c	/* 32 bit ro	Broadcast Frames Xmitted OK */
#define XM_TXF_MC_OK	0x0290	/* 32 bit ro	Multicast Frames Xmitted OK */
#define XM_TXF_UC_OK	0x0294	/* 32 bit ro	Unicast Frames Xmitted OK */
#define XM_TXF_LONG		0x0298	/* 32 bit ro	Tx Long Frame Counter */
#define XM_TXE_BURST	0x029c	/* 32 bit ro	Tx Burst Event Counter */
#define XM_TXF_MPAUSE	0x02a0	/* 32 bit ro	Tx Pause MAC Ctrl Frame Cnt */
#define XM_TXF_MCTRL	0x02a4	/* 32 bit ro	Tx MAC Ctrl Frame Counter */
#define XM_TXF_SNG_COL	0x02a8	/* 32 bit ro	Tx Single Colliosion Counter */
#define XM_TXF_MUL_COL	0x02ac	/* 32 bit ro	Tx Multiple Collision Counter */
#define XM_TXF_ABO_COL	0x02b0	/* 32 bit ro	Tx aborted due to Exessive Col*/
#define XM_TXF_LAT_COL	0x02b4	/* 32 bit ro	Tx Late Collision Counter */
#define XM_TXF_DEF		0x02b8	/* 32 bit ro	Tx Deferred Frame Counter */
#define XM_TXF_EX_DEF	0x02bc	/* 32 bit ro	Tx Excessive Deferall Counter */
#define XM_TXE_FIFO_UR	0x02c0	/* 32 bit ro	Tx FIFO Underrun Event Cnt */
#define XM_TXE_CS_ERR	0x02c4	/* 32 bit ro	Tx Carrier Sence Error Cnt */
#define XM_TXP_UTIL		0x02c8	/* 32 bit ro	Tx Utilization in % */
	/* 0x02cc - 0x02ce:	reserved */
#define XM_TXF_64B		0x02d0	/* 32 bit ro	64 Byte Tx Frame Counter */
#define XM_TXF_127B		0x02d4	/* 32 bit ro	65-127 Byte Tx Frame Counter */
#define XM_TXF_255B		0x02d8	/* 32 bit ro	128-255 Byte Tx Frame Counter */
#define XM_TXF_511B		0x02dc	/* 32 bit ro	256-511 Byte Tx Frame Counter */
#define XM_TXF_1023B	0x02e0	/* 32 bit ro	512-1023 Byte Tx Frame Counter*/
#define XM_TXF_MAX_SZ	0x02e4	/* 32 bit ro	1024-MaxSize Byte Tx Frame Cnt*/
	/* 0x02e8 - 0x02fe:	reserved */
#define XM_RXF_OK		0x0300	/* 32 bit ro	Frames Received OK */
#define XM_RXO_OK_HI	0x0304	/* 32 bit ro	Octets Received OK High Cnt */
#define XM_RXO_OK_LO	0x0308	/* 32 bit ro	Octets Received OK Low Counter*/
#define XM_RXF_BC_OK	0x030c	/* 32 bit ro	Broadcast Frames Received OK */
#define XM_RXF_MC_OK	0x0310	/* 32 bit ro	Multicast Frames Received OK */
#define XM_RXF_UC_OK	0x0314	/* 32 bit ro	Unicast Frames Received OK */
#define XM_RXF_MPAUSE	0x0318	/* 32 bit ro	Rx Pause MAC Ctrl Frame Cnt */
#define XM_RXF_MCTRL	0x031c	/* 32 bit ro	Rx MAC Ctrl Frame Counter */
#define XM_RXF_INV_MP	0x0320	/* 32 bit ro	Rx invalid Pause Frame Cnt */
#define XM_RXF_INV_MOC	0x0324	/* 32 bit ro	Rx Frames with inv. MAC Opcode*/
#define XM_RXE_BURST	0x0328	/* 32 bit ro	Rx Burst Event Counter */
#define XM_RXE_FMISS	0x032c	/* 32 bit ro	Rx Missed Frames Event Cnt */
#define XM_RXF_FRA_ERR	0x0330	/* 32 bit ro	Rx Framing Error Counter */
#define XM_RXE_FIFO_OV	0x0334	/* 32 bit ro	Rx FIFO overflow Event Cnt */
#define XM_RXF_JAB_PKT	0x0338	/* 32 bit ro	Rx Jabber Packet Frame Cnt */
#define XM_RXE_CAR_ERR	0x033c	/* 32 bit ro	Rx Carrier Event Error Cnt */
#define XM_RXF_LEN_ERR	0x0340	/* 32 bit ro	Rx in Range Length Error */
#define XM_RXE_SYM_ERR	0x0344	/* 32 bit ro	Rx Symbol Error Counter */
#define XM_RXE_SHT_ERR	0x0348	/* 32 bit ro	Rx Short Event Error Cnt */
#define XM_RXE_RUNT		0x034c	/* 32 bit ro	Rx Runt Event Counter */
#define XM_RXF_LNG_ERR	0x0350	/* 32 bit ro	Rx Frame too Long Error Cnt */
#define XM_RXF_FCS_ERR	0x0354	/* 32 bit ro	Rx Frame Check Seq. Error Cnt */
	/* 0x0358 - 0x035a:	reserved */
#define XM_RXF_CEX_ERR	0x035c	/* 32 bit ro	Rx Carrier Ext Error Frame Cnt*/
#define XM_RXP_UTIL		0x0360	/* 32 bit ro	Rx Utilization in % */
	/* 0x0364 - 0x0366:	reserved */
#define XM_RXF_64B		0x0368	/* 32 bit ro	64 Byte Rx Frame Counter */
#define XM_RXF_127B		0x036c	/* 32 bit ro	65-127 Byte Rx Frame Counter */
#define XM_RXF_255B		0x0370	/* 32 bit ro	128-255 Byte Rx Frame Counter */
#define XM_RXF_511B		0x0374	/* 32 bit ro	256-511 Byte Rx Frame Counter */
#define XM_RXF_1023B	0x0378	/* 32 bit ro	512-1023 Byte Rx Frame Counter*/
#define XM_RXF_MAX_SZ	0x037c	/* 32 bit ro	1024-MaxSize Byte Rx Frame Cnt*/
	/* 0x02e8 - 0x02fe:	reserved */


/*----------------------------------------------------------------------------*/
/*
 * XMAC Bit Definitions
 *
 * If the bit access behaviour differs from the register access behaviour
 * (r/w, ro) this is docomented after the bit number. The following bit
 * access behaviours are used:
 *	(sc)	self clearing
 *	(ro)	read only
 */

/*	XM_MMU_CMD	16 bit r/w	MMU Comamnd Register */
								/* Bit 15..13:	reserved */
#define XM_MMU_PHY_RDY	(1<<12)	/* Bit 12:	PHY Read Ready */
#define XM_MMU_PHY_BUSY	(1<<11)	/* Bit 11:	PHY Busy */