aic7xxx.reg

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

		mask	SG_HIGH_ADDR_BITS	0x7F	/* In the fourth byte */
	}
	SCB_SGPTR {
		size	4
		bit	SG_RESID_VALID	0x04	/* In the first byte */
		bit	SG_FULL_RESID	0x02	/* In the first byte */
		bit	SG_LIST_NULL	0x01	/* In the first byte */
	}
	SCB_CONTROL {
		size	1
		bit	TARGET_SCB			0x80
		bit	DISCENB				0x40
		bit	TAG_ENB				0x20
		bit	MK_MESSAGE			0x10
		bit	ULTRAENB			0x08
		bit	DISCONNECTED			0x04
		mask	SCB_TAG_TYPE			0x03
	}
	SCB_SCSIID {
		size	1
		bit	TWIN_CHNLB			0x80
		mask	TWIN_TID			0x70
		mask	TID				0xf0
		mask	OID				0x0f
	}
	SCB_LUN {
		mask	LID				0xff
		size	1
	}
	SCB_TAG {
		size	1
	}
	SCB_CDB_LEN {
		size	1
	}
	SCB_SCSIRATE {
		size	1
	}
	SCB_SCSIOFFSET {
		size	1
	}
	SCB_NEXT {
		size	1
	}
	SCB_64_SPARE {
		size	16
	}
	SCB_64_BTT {
		size	16
	}
}

const	SCB_UPLOAD_SIZE		32
const	SCB_DOWNLOAD_SIZE	32
const	SCB_DOWNLOAD_SIZE_64	48

const	SG_SIZEOF	0x08		/* sizeof(struct ahc_dma) */

/* --------------------- AHA-2840-only definitions -------------------- */

register SEECTL_2840 {
	address			0x0c0
	access_mode RW
	bit	CS_2840		0x04
	bit	CK_2840		0x02
	bit	DO_2840		0x01
}

register STATUS_2840 {
	address			0x0c1
	access_mode RW
	bit	EEPROM_TF	0x80
	mask	BIOS_SEL	0x60
	mask	ADSEL		0x1e
	bit	DI_2840		0x01
}

/* --------------------- AIC-7870-only definitions -------------------- */

register CCHADDR {
	address			0x0E0
	size 8
}

register CCHCNT {
	address			0x0E8
}

register CCSGRAM {
	address			0x0E9
}

register CCSGADDR {
	address			0x0EA
}

register CCSGCTL {
	address			0x0EB
	bit	CCSGDONE	0x80
	bit	CCSGEN		0x08
	bit	SG_FETCH_NEEDED 0x02	/* Bit used for software state */
	bit	CCSGRESET	0x01
}

register CCSCBCNT {
	address			0xEF
}

register CCSCBCTL {
	address			0x0EE
	bit	CCSCBDONE	0x80
	bit	ARRDONE		0x40	/* SCB Array prefetch done */
	bit	CCARREN		0x10
	bit	CCSCBEN		0x08
	bit	CCSCBDIR	0x04
	bit	CCSCBRESET	0x01
}

register CCSCBADDR {
	address			0x0ED
}

register CCSCBRAM {
	address			0xEC
}

/*
 * SCB bank address (7895/7896/97 only)
 */
register SCBBADDR {
	address			0x0F0
	access_mode RW
}

register CCSCBPTR {
	address			0x0F1
}

register HNSCB_QOFF {
	address			0x0F4
}

register SNSCB_QOFF {
	address			0x0F6
}

register SDSCB_QOFF {
	address			0x0F8
}

register QOFF_CTLSTA {
	address			0x0FA
	bit	SCB_AVAIL	0x40
	bit	SNSCB_ROLLOVER	0x20
	bit	SDSCB_ROLLOVER	0x10
	mask	SCB_QSIZE	0x07
	mask	SCB_QSIZE_256	0x06
}

register DFF_THRSH {
	address			0x0FB
	mask	WR_DFTHRSH	0x70
	mask	RD_DFTHRSH	0x07
	mask	RD_DFTHRSH_MIN	0x00
	mask	RD_DFTHRSH_25	0x01
	mask	RD_DFTHRSH_50	0x02
	mask	RD_DFTHRSH_63	0x03
	mask	RD_DFTHRSH_75	0x04
	mask	RD_DFTHRSH_85	0x05
	mask	RD_DFTHRSH_90	0x06
	mask	RD_DFTHRSH_MAX	0x07
	mask	WR_DFTHRSH_MIN	0x00
	mask	WR_DFTHRSH_25	0x10
	mask	WR_DFTHRSH_50	0x20
	mask	WR_DFTHRSH_63	0x30
	mask	WR_DFTHRSH_75	0x40
	mask	WR_DFTHRSH_85	0x50
	mask	WR_DFTHRSH_90	0x60
	mask	WR_DFTHRSH_MAX	0x70
}

register SG_CACHE_PRE {
	access_mode WO
	address			0x0fc
	mask	SG_ADDR_MASK	0xf8
	bit	ODD_SEG		0x04
	bit	LAST_SEG	0x02
	bit	LAST_SEG_DONE	0x01
}

register SG_CACHE_SHADOW {
	access_mode RO
	address			0x0fc
	mask	SG_ADDR_MASK	0xf8
	bit	ODD_SEG		0x04
	bit	LAST_SEG	0x02
	bit	LAST_SEG_DONE	0x01
}
/* ---------------------- Scratch RAM Offsets ------------------------- */
/* These offsets are either to values that are initialized by the board's
 * BIOS or are specified by the sequencer code.
 *
 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
 * device information, 32-33 and 5a-5f as well. As it turns out, the
 * BIOS trashes 20-2f, writing the synchronous negotiation results
 * on top of the BIOS values, so we re-use those for our per-target
 * scratchspace (actually a value that can be copied directly into
 * SCSIRATE).  The kernel driver will enable synchronous negotiation
 * for all targets that have a value other than 0 in the lower four
 * bits of the target scratch space.  This should work regardless of
 * whether the bios has been installed.
 */

scratch_ram {
	address			0x020

	/*
	 * 1 byte per target starting at this address for configuration values
	 */
	BUSY_TARGETS {
		alias		TARG_SCSIRATE
		size		16
	}
	/*
	 * Bit vector of targets that have ULTRA enabled as set by
	 * the BIOS.  The Sequencer relies on a per-SCB field to
	 * control whether to enable Ultra transfers or not.  During
	 * initialization, we read this field and reuse it for 2
	 * entries in the busy target table.
	 */
	ULTRA_ENB {
		alias		CMDSIZE_TABLE
		size		2
	}
	/*
	 * Bit vector of targets that have disconnection disabled as set by
	 * the BIOS.  The Sequencer relies in a per-SCB field to control the
	 * disconnect priveldge.  During initialization, we read this field
	 * and reuse it for 2 entries in the busy target table.
	 */
	DISC_DSB {
		size		2
	}
	CMDSIZE_TABLE_TAIL {
		size		4
	}
	/*
	 * Partial transfer past cacheline end to be
	 * transferred using an extra S/G.
	 */
	MWI_RESIDUAL {
		size		1
	}
	/*
	 * SCBID of the next SCB to be started by the controller.
	 */
	NEXT_QUEUED_SCB {
		size		1
	}
	/*
	 * Single byte buffer used to designate the type or message
	 * to send to a target.
	 */
	MSG_OUT {
		size		1
	}
	/* Parameters for DMA Logic */
	DMAPARAMS {
		size		1
		bit	PRELOADEN	0x80
		bit	WIDEODD		0x40
		bit	SCSIEN		0x20
		bit	SDMAEN		0x10
		bit	SDMAENACK	0x10
		bit	HDMAEN		0x08
		bit	HDMAENACK	0x08
		bit	DIRECTION	0x04
		bit	FIFOFLUSH	0x02
		bit	FIFORESET	0x01
	}
	SEQ_FLAGS {
		size		1
		bit	IDENTIFY_SEEN		0x80
		bit	TARGET_CMD_IS_TAGGED	0x40
		bit	DPHASE			0x20
		/* Target flags */
		bit	TARG_CMD_PENDING	0x10
		bit	CMDPHASE_PENDING	0x08
		bit	DPHASE_PENDING		0x04
		bit	SPHASE_PENDING		0x02
		bit	NO_DISCONNECT		0x01
	}
	/*
	 * Temporary storage for the
	 * target/channel/lun of a
	 * reconnecting target
	 */
	SAVED_SCSIID {
		size		1
	}
	SAVED_LUN {
		size		1
	}
	/*
	 * The last bus phase as seen by the sequencer. 
	 */
	LASTPHASE {
		size		1
		bit	CDI		0x80
		bit	IOI		0x40
		bit	MSGI		0x20
		mask	PHASE_MASK	CDI|IOI|MSGI
		mask	P_DATAOUT	0x00
		mask	P_DATAIN	IOI
		mask	P_COMMAND	CDI
		mask	P_MESGOUT	CDI|MSGI
		mask	P_STATUS	CDI|IOI
		mask	P_MESGIN	CDI|IOI|MSGI
		mask	P_BUSFREE	0x01
	}
	/*
	 * head of list of SCBs awaiting
	 * selection
	 */
	WAITING_SCBH {
		size		1
	}
	/*
	 * head of list of SCBs that are
	 * disconnected.  Used for SCB
	 * paging.
	 */
	DISCONNECTED_SCBH {
		size		1
	}
	/*
	 * head of list of SCBs that are
	 * not in use.  Used for SCB paging.
	 */
	FREE_SCBH {
		size		1
	}
	/*
	 * head of list of SCBs that have
	 * completed but have not been
	 * put into the qoutfifo.
	 */
	COMPLETE_SCBH {
		size		1
	}
	/*
	 * Address of the hardware scb array in the host.
	 */
	HSCB_ADDR {
		size		4
	}
	/*
	 * Base address of our shared data with the kernel driver in host
	 * memory.  This includes the qoutfifo and target mode
	 * incoming command queue.
	 */
	SHARED_DATA_ADDR {
		size		4
	}
	KERNEL_QINPOS {
		size		1
	}
	QINPOS {
		size		1
	}
	QOUTPOS {
		size		1
	}
	/*
	 * Kernel and sequencer offsets into the queue of
	 * incoming target mode command descriptors.  The
	 * queue is full when the KERNEL_TQINPOS == TQINPOS.
	 */
	KERNEL_TQINPOS {
		size		1
	}
	TQINPOS {                
		size		1
	}
	ARG_1 {
		size		1
		mask	SEND_MSG		0x80
		mask	SEND_SENSE		0x40
		mask	SEND_REJ		0x20
		mask	MSGOUT_PHASEMIS		0x10
		mask	EXIT_MSG_LOOP		0x08
		mask	CONT_MSG_LOOP		0x04
		mask	CONT_TARG_SESSION	0x02
		alias	RETURN_1
	}
	ARG_2 {
		size		1
		alias	RETURN_2
	}

	/*
	 * Snapshot of MSG_OUT taken after each message is sent.
	 */
	LAST_MSG {
		size		1
	}

	/*
	 * Sequences the kernel driver has okayed for us.  This allows
	 * the driver to do things like prevent initiator or target
	 * operations.
	 */
	SCSISEQ_TEMPLATE {
		size		1
		bit	ENSELO		0x40
		bit	ENSELI		0x20
		bit	ENRSELI		0x10
		bit	ENAUTOATNO	0x08
		bit	ENAUTOATNI	0x04
		bit	ENAUTOATNP	0x02
	}

	/*
	 * Track whether the transfer byte count for
	 * the current data phase is odd.
	 */
	DATA_COUNT_ODD {
		size		1
	}

	/*
	 * The initiator specified tag for this target mode transaction.
	 */
	INITIATOR_TAG {
		size		1
	}

	SEQ_FLAGS2 {
		size		1
		bit	SCB_DMA			  0x01
		bit	TARGET_MSG_PENDING	  0x02
	}
	/*
	 * These are reserved registers in the card's scratch ram.  Some of
	 * the values are specified in the AHA2742 technical reference manual
	 * and are initialized by the BIOS at boot time.
	 */
	SCSICONF {
		address		0x05a
		size		1
		bit	TERM_ENB	0x80
		bit	RESET_SCSI	0x40
		bit	ENSPCHK		0x20
		mask	HSCSIID		0x07	/* our SCSI ID */
		mask	HWSCSIID	0x0f	/* our SCSI ID if Wide Bus */
	}
	INTDEF {
		address		0x05c
		size		1
		bit	EDGE_TRIG	0x80
		mask	VECTOR		0x0f
	}
	HOSTCONF {
		address		0x05d
		size		1
	}
	HA_274_BIOSCTRL	{
		address		0x05f
		size		1
		mask	BIOSMODE		0x30
		mask	BIOSDISABLED		0x30	
		bit	CHANNEL_B_PRIMARY	0x08
	}
	/*
	 * Per target SCSI offset values for Ultra2 controllers.
	 */
	TARG_OFFSET {
		address		0x070
		size		16
	}
}

const TID_SHIFT		4
const SCB_LIST_NULL	0xff
const TARGET_CMD_CMPLT	0xfe

const CCSGADDR_MAX	0x80
const CCSGRAM_MAXSEGS	16

/* WDTR Message values */
const BUS_8_BIT			0x00
const BUS_16_BIT		0x01
const BUS_32_BIT		0x02

/* Offset maximums */
const MAX_OFFSET_8BIT		0x0f
const MAX_OFFSET_16BIT		0x08
const MAX_OFFSET_ULTRA2		0x7f
const HOST_MSG			0xff

/* Target mode command processing constants */
const CMD_GROUP_CODE_SHIFT	0x05

const STATUS_BUSY		0x08
const STATUS_QUEUE_FULL	0x28
const TARGET_DATA_IN		1

/*
 * Downloaded (kernel inserted) constants
 */
/* Offsets into the SCBID array where different data is stored */
const QOUTFIFO_OFFSET download
const QINFIFO_OFFSET download
const CACHESIZE_MASK download
const INVERTED_CACHESIZE_MASK download
const SG_PREFETCH_CNT download
const SG_PREFETCH_ALIGN_MASK download
const SG_PREFETCH_ADDR_MASK download