aic7xxx.reg

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

/*
 * Aic7xxx register and scratch ram definitions.
 *
 * Copyright (c) 1994-2001 Justin T. Gibbs.
 * Copyright (c) 2000-2001 Adaptec Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    substantially similar to the "NO WARRANTY" disclaimer below
 *    ("Disclaimer") and any redistribution must be conditioned upon
 *    including a substantially similar Disclaimer requirement for further
 *    binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES.
 *
 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.31 2000/11/10 20:13:40 gibbs Exp $
 */
VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#24 $"

/*
 * This file is processed by the aic7xxx_asm utility for use in assembling
 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
 * a C header file for use in the kernel portion of the Aic7xxx driver.
 *
 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
 * Adaptec's Technical Documents Department 1-800-934-2766
 */

/*
 * SCSI Sequence Control (p. 3-11).
 * Each bit, when set starts a specific SCSI sequence on the bus
 */
register SCSISEQ {
	address			0x000
	access_mode RW
	bit	TEMODE		0x80
	bit	ENSELO		0x40
	bit	ENSELI		0x20
	bit	ENRSELI		0x10
	bit	ENAUTOATNO	0x08
	bit	ENAUTOATNI	0x04
	bit	ENAUTOATNP	0x02
	bit	SCSIRSTO	0x01
}

/*
 * SCSI Transfer Control 0 Register (pp. 3-13).
 * Controls the SCSI module data path.
 */
register SXFRCTL0 {
	address			0x001
	access_mode RW
	bit	DFON		0x80
	bit	DFPEXP		0x40
	bit	FAST20		0x20
	bit	CLRSTCNT	0x10
	bit	SPIOEN		0x08
	bit	SCAMEN		0x04
	bit	CLRCHN		0x02
}

/*
 * SCSI Transfer Control 1 Register (pp. 3-14,15).
 * Controls the SCSI module data path.
 */
register SXFRCTL1 {
	address			0x002
	access_mode RW
	bit	BITBUCKET	0x80
	bit	SWRAPEN		0x40
	bit	ENSPCHK		0x20
	mask	STIMESEL	0x18
	bit	ENSTIMER	0x04
	bit	ACTNEGEN	0x02
	bit	STPWEN		0x01	/* Powered Termination */
}

/*
 * SCSI Control Signal Read Register (p. 3-15).
 * Reads the actual state of the SCSI bus pins
 */
register SCSISIGI {
	address			0x003
	access_mode RO
	bit	CDI		0x80
	bit	IOI		0x40
	bit	MSGI		0x20
	bit	ATNI		0x10
	bit	SELI		0x08
	bit	BSYI		0x04
	bit	REQI		0x02
	bit	ACKI		0x01
/*
 * Possible phases in SCSISIGI
 */
	mask	PHASE_MASK	CDI|IOI|MSGI
	mask	P_DATAOUT	0x00
	mask	P_DATAIN	IOI
	mask	P_DATAOUT_DT	P_DATAOUT|MSGI
	mask	P_DATAIN_DT	P_DATAIN|MSGI
	mask	P_COMMAND	CDI
	mask	P_MESGOUT	CDI|MSGI
	mask	P_STATUS	CDI|IOI
	mask	P_MESGIN	CDI|IOI|MSGI
}

/*
 * SCSI Control Signal Write Register (p. 3-16).
 * Writing to this register modifies the control signals on the bus.  Only
 * those signals that are allowed in the current mode (Initiator/Target) are
 * asserted.
 */
register SCSISIGO {
	address			0x003
	access_mode WO
	bit	CDO		0x80
	bit	IOO		0x40
	bit	MSGO		0x20
	bit	ATNO		0x10
	bit	SELO		0x08
	bit	BSYO		0x04
	bit	REQO		0x02
	bit	ACKO		0x01
/*
 * Possible phases to write into SCSISIG0
 */
	mask	PHASE_MASK	CDI|IOI|MSGI
	mask	P_DATAOUT	0x00
	mask	P_DATAIN	IOI
	mask	P_COMMAND	CDI
	mask	P_MESGOUT	CDI|MSGI
	mask	P_STATUS	CDI|IOI
	mask	P_MESGIN	CDI|IOI|MSGI
}

/* 
 * SCSI Rate Control (p. 3-17).
 * Contents of this register determine the Synchronous SCSI data transfer
 * rate and the maximum synchronous Req/Ack offset.  An offset of 0 in the
 * SOFS (3:0) bits disables synchronous data transfers.  Any offset value
 * greater than 0 enables synchronous transfers.
 */
register SCSIRATE {
	address			0x004
	access_mode RW
	bit	WIDEXFER	0x80		/* Wide transfer control */
	bit	ENABLE_CRC	0x40		/* CRC for D-Phases */
	bit	SINGLE_EDGE	0x10		/* Disable DT Transfers */
	mask	SXFR		0x70		/* Sync transfer rate */
	mask	SXFR_ULTRA2	0x0f		/* Sync transfer rate */
	mask	SOFS		0x0f		/* Sync offset */
}

/*
 * SCSI ID (p. 3-18).
 * Contains the ID of the board and the current target on the
 * selected channel.
 */
register SCSIID	{
	address			0x005
	access_mode RW
	mask	TID		0xf0		/* Target ID mask */
	mask	TWIN_TID	0x70
	bit	TWIN_CHNLB	0x80
	mask	OID		0x0f		/* Our ID mask */
	/*
	 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
	 * The aic7890/91 allow an offset of up to 127 transfers in both wide
	 * and narrow mode.
	 */
	alias	SCSIOFFSET
	mask	SOFS_ULTRA2	0x7f		/* Sync offset U2 chips */
}

/*
 * SCSI Latched Data (p. 3-19).
 * Read/Write latches used to transfer data on the SCSI bus during
 * Automatic or Manual PIO mode.  SCSIDATH can be used for the
 * upper byte of a 16bit wide asynchronouse data phase transfer.
 */
register SCSIDATL {
	address			0x006
	access_mode RW
}

register SCSIDATH {
	address			0x007
	access_mode RW
}

/*
 * SCSI Transfer Count (pp. 3-19,20)
 * These registers count down the number of bytes transferred
 * across the SCSI bus.  The counter is decremented only once
 * the data has been safely transferred.  SDONE in SSTAT0 is
 * set when STCNT goes to 0
 */ 
register STCNT {
	address			0x008
	size	3
	access_mode RW
}

/* ALT_MODE register on Ultra160 chips */
register OPTIONMODE {
	address			0x008
	access_mode RW
	bit	AUTORATEEN		0x80
	bit	AUTOACKEN		0x40
	bit	ATNMGMNTEN		0x20
	bit	BUSFREEREV		0x10
	bit	EXPPHASEDIS		0x08
	bit	SCSIDATL_IMGEN		0x04
	bit	AUTO_MSGOUT_DE		0x02
	bit	DIS_MSGIN_DUALEDGE	0x01
	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
}

/* ALT_MODE register on Ultra160 chips */
register TARGCRCCNT {
	address			0x00a
	size	2
	access_mode RW
}

/*
 * Clear SCSI Interrupt 0 (p. 3-20)
 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
 */
register CLRSINT0 {
	address			0x00b
	access_mode WO
	bit	CLRSELDO	0x40
	bit	CLRSELDI	0x20
	bit	CLRSELINGO	0x10
	bit	CLRSWRAP	0x08
	bit	CLRIOERR	0x08	/* Ultra2 Only */
	bit	CLRSPIORDY	0x02
}

/*
 * SCSI Status 0 (p. 3-21)
 * Contains one set of SCSI Interrupt codes
 * These are most likely of interest to the sequencer
 */
register SSTAT0	{
	address			0x00b
	access_mode RO
	bit	TARGET		0x80	/* Board acting as target */
	bit	SELDO		0x40	/* Selection Done */
	bit	SELDI		0x20	/* Board has been selected */
	bit	SELINGO		0x10	/* Selection In Progress */
	bit	SWRAP		0x08	/* 24bit counter wrap */
	bit	IOERR		0x08	/* LVD Tranceiver mode changed */
	bit	SDONE		0x04	/* STCNT = 0x000000 */
	bit	SPIORDY		0x02	/* SCSI PIO Ready */
	bit	DMADONE		0x01	/* DMA transfer completed */
}

/*
 * Clear SCSI Interrupt 1 (p. 3-23)
 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 */
register CLRSINT1 {
	address			0x00c
	access_mode WO
	bit	CLRSELTIMEO	0x80
	bit	CLRATNO		0x40
	bit	CLRSCSIRSTI	0x20
	bit	CLRBUSFREE	0x08
	bit	CLRSCSIPERR	0x04
	bit	CLRPHASECHG	0x02
	bit	CLRREQINIT	0x01
}

/*
 * SCSI Status 1 (p. 3-24)
 */
register SSTAT1	{
	address			0x00c
	access_mode RO
	bit	SELTO		0x80
	bit	ATNTARG 	0x40
	bit	SCSIRSTI	0x20
	bit	PHASEMIS	0x10
	bit	BUSFREE		0x08
	bit	SCSIPERR	0x04
	bit	PHASECHG	0x02
	bit	REQINIT		0x01
}

/*
 * SCSI Status 2 (pp. 3-25,26)
 */
register SSTAT2 {
	address			0x00d
	access_mode RO
	bit	OVERRUN		0x80
	bit	SHVALID		0x40	/* Shaddow Layer non-zero */
	bit	EXP_ACTIVE	0x10	/* SCSI Expander Active */
	bit	CRCVALERR	0x08	/* CRC doesn't match (U3 only) */
	bit	CRCENDERR	0x04	/* No terminal CRC packet (U3 only) */
	bit	CRCREQERR	0x02	/* Illegal CRC packet req (U3 only) */
	bit	DUAL_EDGE_ERR	0x01	/* Incorrect data phase (U3 only) */
	mask	SFCNT		0x1f
}

/*
 * SCSI Status 3 (p. 3-26)
 */
register SSTAT3 {
	address			0x00e
	access_mode RO
	mask	SCSICNT		0xf0
	mask	OFFCNT		0x0f
	mask	U2OFFCNT	0x7f
}

/*
 * SCSI ID for the aic7890/91 chips
 */
register SCSIID_ULTRA2 {
	address			0x00f
	access_mode RW
	mask	TID		0xf0		/* Target ID mask */
	mask	OID		0x0f		/* Our ID mask */
}

/*
 * SCSI Interrupt Mode 1 (p. 3-28)
 * Setting any bit will enable the corresponding function
 * in SIMODE0 to interrupt via the IRQ pin.
 */
register SIMODE0 {
	address			0x010
	access_mode RW
	bit	ENSELDO		0x40
	bit	ENSELDI		0x20
	bit	ENSELINGO	0x10
	bit	ENSWRAP		0x08
	bit	ENIOERR		0x08	/* LVD Tranceiver mode changes */
	bit	ENSDONE		0x04
	bit	ENSPIORDY	0x02
	bit	ENDMADONE	0x01
}

/*
 * SCSI Interrupt Mode 1 (pp. 3-28,29)
 * Setting any bit will enable the corresponding function
 * in SIMODE1 to interrupt via the IRQ pin.
 */
register SIMODE1 {
	address			0x011
	access_mode RW
	bit	ENSELTIMO	0x80
	bit	ENATNTARG	0x40
	bit	ENSCSIRST	0x20
	bit	ENPHASEMIS	0x10
	bit	ENBUSFREE	0x08
	bit	ENSCSIPERR	0x04
	bit	ENPHASECHG	0x02
	bit	ENREQINIT	0x01
}

/*
 * SCSI Data Bus (High) (p. 3-29)
 * This register reads data on the SCSI Data bus directly.
 */
register SCSIBUSL {
	address			0x012
	access_mode RW
}

register SCSIBUSH {
	address			0x013
	access_mode RW
}

/*
 * SCSI/Host Address (p. 3-30)
 * These registers hold the host address for the byte about to be
 * transferred on the SCSI bus.  They are counted up in the same
 * manner as STCNT is counted down.  SHADDR should always be used
 * to determine the address of the last byte transferred since HADDR
 * can be skewed by write ahead.
 */
register SHADDR {
	address			0x014
	size	4
	access_mode RO
}

/*
 * Selection Timeout Timer (p. 3-30)
 */
register SELTIMER {
	address			0x018
	access_mode RW
	bit	STAGE6		0x20
	bit	STAGE5		0x10
	bit	STAGE4		0x08
	bit	STAGE3		0x04
	bit	STAGE2		0x02
	bit	STAGE1		0x01
	alias	TARGIDIN
}

/*
 * Selection/Reselection ID (p. 3-31)
 * Upper four bits are the device id.  The ONEBIT is set when the re/selecting
 * device did not set its own ID.
 */
register SELID {
	address			0x019
	access_mode RW
	mask	SELID_MASK	0xf0
	bit	ONEBIT		0x08
}

register SCAMCTL {
	address			0x01a
	access_mode RW
	bit	ENSCAMSELO	0x80
	bit	CLRSCAMSELID	0x40
	bit	ALTSTIM		0x20
	bit	DFLTTID		0x10
	mask	SCAMLVL		0x03
}

/*
 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
 */
register TARGID {
	address			0x01b
	size			2
	access_mode RW
}

/*
 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
 * Indicates if external logic has been attached to the chip to
 * perform the tasks of accessing a serial eeprom, testing termination
 * strength, and performing cable detection.  On the aic7860, most of
 * these features are handled on chip, but on the aic7855 an attached
 * aic3800 does the grunt work.
 */
register SPIOCAP {
	address			0x01b
	access_mode RW
	bit	SOFT1		0x80
	bit	SOFT0		0x40
	bit	SOFTCMDEN	0x20	
	bit	HAS_BRDCTL	0x10	/* External Board control */
	bit	SEEPROM		0x08	/* External serial eeprom logic */
	bit	EEPROM		0x04	/* Writable external BIOS ROM */
	bit	ROM		0x02	/* Logic for accessing external ROM */
	bit	SSPIOCPS	0x01	/* Termination and cable detection */
}

register BRDCTL	{
	address			0x01d
	bit	BRDDAT7		0x80
	bit	BRDDAT6		0x40
	bit	BRDDAT5		0x20
	bit	BRDSTB		0x10
	bit	BRDCS		0x08
	bit	BRDRW		0x04
	bit	BRDCTL1		0x02
	bit	BRDCTL0		0x01
	/* 7890 Definitions */
	bit	BRDDAT4		0x10
	bit	BRDDAT3		0x08
	bit	BRDDAT2		0x04
	bit	BRDRW_ULTRA2	0x02
	bit	BRDSTB_ULTRA2	0x01
}

/*
 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 * Controls the reading and writing of an external serial 1-bit
 * EEPROM Device.  In order to access the serial EEPROM, you must
 * first set the SEEMS bit that generates a request to the memory
 * port for access to the serial EEPROM device.  When the memory
 * port is not busy servicing another request, it reconfigures
 * to allow access to the serial EEPROM.  When this happens, SEERDY
 * gets set high to verify that the memory port access has been
 * granted.  
 *
 * After successful arbitration for the memory port, the SEECS bit of 
 * the SEECTL register is connected to the chip select.  The SEECK, 
 * SEEDO, and SEEDI are connected to the clock, data out, and data in 
 * lines respectively.  The SEERDY bit of SEECTL is useful in that it 
 * gives us an 800 nsec timer.  After a write to the SEECTL register, 
 * the SEERDY goes high 800 nsec later.  The one exception to this is 
 * when we first request access to the memory port.  The SEERDY goes 
 * high to signify that access has been granted and, for this case, has 
 * no implied timing.