📄 radeon_drv.h

📁 内核linux2.4.20,可跟rtlinux3.2打补丁组成实时linux系统,编译内核
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/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Fremont, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: *    Kevin E. Martin <martin@valinux.com> *    Gareth Hughes <gareth@valinux.com> */#ifndef __RADEON_DRV_H__#define __RADEON_DRV_H__typedef struct drm_radeon_freelist {   	unsigned int age;   	drm_buf_t *buf;   	struct drm_radeon_freelist *next;   	struct drm_radeon_freelist *prev;} drm_radeon_freelist_t;typedef struct drm_radeon_ring_buffer {	u32 *start;	u32 *end;	int size;	int size_l2qw;	volatile u32 *head;	u32 tail;	u32 tail_mask;	int space;	int high_mark;} drm_radeon_ring_buffer_t;typedef struct drm_radeon_depth_clear_t {	u32 rb3d_cntl;	u32 rb3d_zstencilcntl;	u32 se_cntl;} drm_radeon_depth_clear_t;typedef struct drm_radeon_private {	drm_radeon_ring_buffer_t ring;	drm_radeon_sarea_t *sarea_priv;	int agp_size;	u32 agp_vm_start;	unsigned long agp_buffers_offset;	int cp_mode;	int cp_running;   	drm_radeon_freelist_t *head;   	drm_radeon_freelist_t *tail;/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist   code is used.  Note this hides a problem with the scratch register   (used to keep track of last buffer completed) being written to before   the last buffer has actually completed rendering. */#define ROTATE_BUFS 1#if ROTATE_BUFS	int last_buf;#endif	volatile u32 *scratch;	int usec_timeout;	int is_pci;	unsigned long phys_pci_gart;	dma_addr_t bus_pci_gart;	atomic_t idle_count;	int page_flipping;	int current_page;	u32 crtc_offset;	u32 crtc_offset_cntl;	u32 color_fmt;	unsigned int front_offset;	unsigned int front_pitch;	unsigned int back_offset;	unsigned int back_pitch;	u32 depth_fmt;	unsigned int depth_offset;	unsigned int depth_pitch;	u32 front_pitch_offset;	u32 back_pitch_offset;	u32 depth_pitch_offset;	drm_radeon_depth_clear_t depth_clear;	drm_map_t *sarea;	drm_map_t *fb;	drm_map_t *mmio;	drm_map_t *cp_ring;	drm_map_t *ring_rptr;	drm_map_t *buffers;	drm_map_t *agp_textures;} drm_radeon_private_t;typedef struct drm_radeon_buf_priv {	u32 age;	int prim;	int discard;	int dispatched;   	drm_radeon_freelist_t *list_entry;} drm_radeon_buf_priv_t;				/* radeon_cp.c */extern int radeon_cp_init( struct inode *inode, struct file *filp,			   unsigned int cmd, unsigned long arg );extern int radeon_cp_start( struct inode *inode, struct file *filp,			    unsigned int cmd, unsigned long arg );extern int radeon_cp_stop( struct inode *inode, struct file *filp,			   unsigned int cmd, unsigned long arg );extern int radeon_cp_reset( struct inode *inode, struct file *filp,			    unsigned int cmd, unsigned long arg );extern int radeon_cp_idle( struct inode *inode, struct file *filp,			   unsigned int cmd, unsigned long arg );extern int radeon_engine_reset( struct inode *inode, struct file *filp,				unsigned int cmd, unsigned long arg );extern int radeon_fullscreen( struct inode *inode, struct file *filp,			      unsigned int cmd, unsigned long arg );extern int radeon_cp_buffers( struct inode *inode, struct file *filp,			      unsigned int cmd, unsigned long arg );extern void radeon_freelist_reset( drm_device_t *dev );extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );static inline voidradeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring ){	ring->space = (*(volatile int *)ring->head - ring->tail) * sizeof(u32);	if ( ring->space <= 0 )		ring->space += ring->size;}extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );extern int radeon_do_cleanup_cp( drm_device_t *dev );extern int radeon_do_cleanup_pageflip( drm_device_t *dev );				/* radeon_state.c */extern int radeon_cp_clear( struct inode *inode, struct file *filp,			    unsigned int cmd, unsigned long arg );extern int radeon_cp_swap( struct inode *inode, struct file *filp,			   unsigned int cmd, unsigned long arg );extern int radeon_cp_vertex( struct inode *inode, struct file *filp,			     unsigned int cmd, unsigned long arg );extern int radeon_cp_indices( struct inode *inode, struct file *filp,			      unsigned int cmd, unsigned long arg );extern int radeon_cp_texture( struct inode *inode, struct file *filp,			      unsigned int cmd, unsigned long arg );extern int radeon_cp_stipple( struct inode *inode, struct file *filp,			      unsigned int cmd, unsigned long arg );extern int radeon_cp_indirect( struct inode *inode, struct file *filp,			       unsigned int cmd, unsigned long arg );/* Register definitions, register access macros and drmAddMap constants * for Radeon kernel driver. */#define RADEON_AGP_COMMAND		0x0f60#define RADEON_AUX_SCISSOR_CNTL		0x26f0#	define RADEON_EXCLUSIVE_SCISSOR_0	(1 << 24)#	define RADEON_EXCLUSIVE_SCISSOR_1	(1 << 25)#	define RADEON_EXCLUSIVE_SCISSOR_2	(1 << 26)#	define RADEON_SCISSOR_0_ENABLE		(1 << 28)#	define RADEON_SCISSOR_1_ENABLE		(1 << 29)#	define RADEON_SCISSOR_2_ENABLE		(1 << 30)#define RADEON_BUS_CNTL			0x0030#	define RADEON_BUS_MASTER_DIS		(1 << 6)#define RADEON_CLOCK_CNTL_DATA		0x000c#	define RADEON_PLL_WR_EN			(1 << 7)#define RADEON_CLOCK_CNTL_INDEX		0x0008#define RADEON_CONFIG_APER_SIZE		0x0108#define RADEON_CRTC_OFFSET		0x0224#define RADEON_CRTC_OFFSET_CNTL		0x0228#	define RADEON_CRTC_TILE_EN		(1 << 15)#	define RADEON_CRTC_OFFSET_FLIP_CNTL	(1 << 16)#define RADEON_RB3D_COLORPITCH		0x1c48#define RADEON_RB3D_DEPTHCLEARVALUE	0x1c30#define RADEON_RB3D_DEPTHXY_OFFSET	0x1c60#define RADEON_DP_GUI_MASTER_CNTL	0x146c#	define RADEON_GMC_SRC_PITCH_OFFSET_CNTL	(1 << 0)#	define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1 << 1)#	define RADEON_GMC_BRUSH_SOLID_COLOR	(13 << 4)#	define RADEON_GMC_BRUSH_NONE		(15 << 4)#	define RADEON_GMC_DST_16BPP		(4 << 8)#	define RADEON_GMC_DST_24BPP		(5 << 8)#	define RADEON_GMC_DST_32BPP		(6 << 8)#	define RADEON_GMC_DST_DATATYPE_SHIFT	8#	define RADEON_GMC_SRC_DATATYPE_COLOR	(3 << 12)#	define RADEON_DP_SRC_SOURCE_MEMORY	(2 << 24)#	define RADEON_DP_SRC_SOURCE_HOST_DATA	(3 << 24)#	define RADEON_GMC_CLR_CMP_CNTL_DIS	(1 << 28)#	define RADEON_GMC_WR_MSK_DIS		(1 << 30)#	define RADEON_ROP3_S			0x00cc0000#	define RADEON_ROP3_P			0x00f00000#define RADEON_DP_WRITE_MASK		0x16cc#define RADEON_DST_PITCH_OFFSET		0x142c#define RADEON_DST_PITCH_OFFSET_C	0x1c80#	define RADEON_DST_TILE_LINEAR		(0 << 30)#	define RADEON_DST_TILE_MACRO		(1 << 30)#	define RADEON_DST_TILE_MICRO		(2 << 30)#	define RADEON_DST_TILE_BOTH		(3 << 30)#define RADEON_SCRATCH_REG0		0x15e0#define RADEON_SCRATCH_REG1		0x15e4#define RADEON_SCRATCH_REG2		0x15e8#define RADEON_SCRATCH_REG3		0x15ec#define RADEON_SCRATCH_REG4		0x15f0#define RADEON_SCRATCH_REG5		0x15f4#define RADEON_SCRATCH_UMSK		0x0770#define RADEON_SCRATCH_ADDR		0x0774#define RADEON_HOST_PATH_CNTL		0x0130#	define RADEON_HDP_SOFT_RESET		(1 << 26)#	define RADEON_HDP_WC_TIMEOUT_MASK	(7 << 28)#	define RADEON_HDP_WC_TIMEOUT_28BCLK	(7 << 28)#define RADEON_ISYNC_CNTL		0x1724#	define RADEON_ISYNC_ANY2D_IDLE3D	(1 << 0)#	define RADEON_ISYNC_ANY3D_IDLE2D	(1 << 1)#	define RADEON_ISYNC_TRIG2D_IDLE3D	(1 << 2)#	define RADEON_ISYNC_TRIG3D_IDLE2D	(1 << 3)#	define RADEON_ISYNC_WAIT_IDLEGUI	(1 << 4)#	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)#define RADEON_MC_AGP_LOCATION		0x014c#define RADEON_MC_FB_LOCATION		0x0148#define RADEON_MCLK_CNTL		0x0012#	define RADEON_FORCEON_MCLKA		(1 << 16)#	define RADEON_FORCEON_MCLKB		(1 << 17)#	define RADEON_FORCEON_YCLKA		(1 << 18)#	define RADEON_FORCEON_YCLKB		(1 << 19)#	define RADEON_FORCEON_MC		(1 << 20)#	define RADEON_FORCEON_AIC		(1 << 21)#define RADEON_PP_BORDER_COLOR_0	0x1d40#define RADEON_PP_BORDER_COLOR_1	0x1d44#define RADEON_PP_BORDER_COLOR_2	0x1d48#define RADEON_PP_CNTL			0x1c38#	define RADEON_SCISSOR_ENABLE		(1 <<  1)#define RADEON_PP_LUM_MATRIX		0x1d00#define RADEON_PP_MISC			0x1c14#define RADEON_PP_ROT_MATRIX_0		0x1d58#define RADEON_PP_TXFILTER_0		0x1c54#define RADEON_PP_TXFILTER_1		0x1c6c#define RADEON_PP_TXFILTER_2		0x1c84#define RADEON_RB2D_DSTCACHE_CTLSTAT	0x342c#	define RADEON_RB2D_DC_FLUSH		(3 << 0)#	define RADEON_RB2D_DC_FREE		(3 << 2)#	define RADEON_RB2D_DC_FLUSH_ALL		0xf#	define RADEON_RB2D_DC_BUSY		(1 << 31)#define RADEON_RB3D_CNTL		0x1c3c#	define RADEON_ALPHA_BLEND_ENABLE	(1 << 0)#	define RADEON_PLANE_MASK_ENABLE		(1 << 1)#	define RADEON_DITHER_ENABLE		(1 << 2)#	define RADEON_ROUND_ENABLE		(1 << 3)#	define RADEON_SCALE_DITHER_ENABLE	(1 << 4)#	define RADEON_DITHER_INIT		(1 << 5)#	define RADEON_ROP_ENABLE		(1 << 6)#	define RADEON_STENCIL_ENABLE		(1 << 7)#	define RADEON_Z_ENABLE			(1 << 8)#	define RADEON_DEPTH_XZ_OFFEST_ENABLE	(1 << 9)#	define RADEON_ZBLOCK8			(0 << 15)#	define RADEON_ZBLOCK16			(1 << 15)#define RADEON_RB3D_DEPTHOFFSET		0x1c24#define RADEON_RB3D_PLANEMASK		0x1d84#define RADEON_RB3D_STENCILREFMASK	0x1d7c#define RADEON_RB3D_ZCACHE_MODE		0x3250#define RADEON_RB3D_ZCACHE_CTLSTAT	0x3254#	define RADEON_RB3D_ZC_FLUSH		(1 << 0)#	define RADEON_RB3D_ZC_FREE		(1 << 2)#	define RADEON_RB3D_ZC_FLUSH_ALL		0x5#	define RADEON_RB3D_ZC_BUSY		(1 << 31)#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c#	define RADEON_Z_TEST_MASK		(7 << 4)#	define RADEON_Z_TEST_ALWAYS		(7 << 4)#	define RADEON_STENCIL_TEST_ALWAYS	(7 << 12)#	define RADEON_STENCIL_S_FAIL_KEEP	(0 << 16)#	define RADEON_STENCIL_ZPASS_KEEP	(0 << 20)#	define RADEON_STENCIL_ZFAIL_KEEP	(0 << 20)#	define RADEON_Z_WRITE_ENABLE		(1 << 30)#define RADEON_RBBM_SOFT_RESET		0x00f0#	define RADEON_SOFT_RESET_CP		(1 <<  0)#	define RADEON_SOFT_RESET_HI		(1 <<  1)#	define RADEON_SOFT_RESET_SE		(1 <<  2)#	define RADEON_SOFT_RESET_RE		(1 <<  3)#	define RADEON_SOFT_RESET_PP		(1 <<  4)#	define RADEON_SOFT_RESET_E2		(1 <<  5)#	define RADEON_SOFT_RESET_RB		(1 <<  6)#	define RADEON_SOFT_RESET_HDP		(1 <<  7)#define RADEON_RBBM_STATUS		0x0e40#	define RADEON_RBBM_FIFOCNT_MASK		0x007f#	define RADEON_RBBM_ACTIVE		(1 << 31)#define RADEON_RE_LINE_PATTERN		0x1cd0#define RADEON_RE_MISC			0x26c4#define RADEON_RE_TOP_LEFT		0x26c0#define RADEON_RE_WIDTH_HEIGHT		0x1c44#define RADEON_RE_STIPPLE_ADDR		0x1cc8#define RADEON_RE_STIPPLE_DATA		0x1ccc#define RADEON_SCISSOR_TL_0		0x1cd8#define RADEON_SCISSOR_BR_0		0x1cdc#define RADEON_SCISSOR_TL_1		0x1ce0#define RADEON_SCISSOR_BR_1		0x1ce4#define RADEON_SCISSOR_TL_2		0x1ce8#define RADEON_SCISSOR_BR_2		0x1cec#define RADEON_SE_COORD_FMT		0x1c50#define RADEON_SE_CNTL			0x1c4c#	define RADEON_FFACE_CULL_CW		(0 << 0)#	define RADEON_BFACE_SOLID		(3 << 1)#	define RADEON_FFACE_SOLID		(3 << 3)#	define RADEON_FLAT_SHADE_VTX_LAST	(3 << 6)#	define RADEON_DIFFUSE_SHADE_FLAT	(1 << 8)#	define RADEON_DIFFUSE_SHADE_GOURAUD	(2 << 8)#	define RADEON_ALPHA_SHADE_FLAT		(1 << 10)#	define RADEON_ALPHA_SHADE_GOURAUD	(2 << 10)#	define RADEON_SPECULAR_SHADE_FLAT	(1 << 12)#	define RADEON_SPECULAR_SHADE_GOURAUD	(2 << 12)#	define RADEON_FOG_SHADE_FLAT		(1 << 14)#	define RADEON_FOG_SHADE_GOURAUD		(2 << 14)#	define RADEON_VPORT_XY_XFORM_ENABLE	(1 << 24)#	define RADEON_VPORT_Z_XFORM_ENABLE	(1 << 25)#	define RADEON_VTX_PIX_CENTER_OGL	(1 << 27)#	define RADEON_ROUND_MODE_TRUNC		(0 << 28)#	define RADEON_ROUND_PREC_8TH_PIX	(1 << 30)#define RADEON_SE_CNTL_STATUS		0x2140#define RADEON_SE_LINE_WIDTH		0x1db8#define RADEON_SE_VPORT_XSCALE		0x1d98#define RADEON_SURFACE_ACCESS_FLAGS	0x0bf8#define RADEON_SURFACE_ACCESS_CLR	0x0bfc#define RADEON_SURFACE_CNTL		0x0b00#	define RADEON_SURF_TRANSLATION_DIS	(1 << 8)#	define RADEON_NONSURF_AP0_SWP_MASK	(3 << 20)#	define RADEON_NONSURF_AP0_SWP_LITTLE	(0 << 20)#	define RADEON_NONSURF_AP0_SWP_BIG16	(1 << 20)#	define RADEON_NONSURF_AP0_SWP_BIG32	(2 << 20)#	define RADEON_NONSURF_AP1_SWP_MASK	(3 << 22)#	define RADEON_NONSURF_AP1_SWP_LITTLE	(0 << 22)#	define RADEON_NONSURF_AP1_SWP_BIG16	(1 << 22)
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